IP Library › Assignment 009845/0188
Patent Assignment
Reel/Frame 009845/0188

Assignment of Assignor's Interest

Recorded: 1999-04-02 Pages: 15
Assignor
Assignee
SHARP LABORATORIES OF AMERICA, INC.
5750 N.W. PACIFIC RIM BLVD., CAMAS, WASHINGTON, 98607
Covered Properties (111)
Apparatus and Method for Locating Mobile and Portable Radio Terminals in a Radio Network
Patent: 5,293,645 →
Application: 07/771,195 →
Trilayer Lithographic Process
Patent: 5,370,969 →
Application: 07/922,983 →
Lithographic Process for Producing Small Mask Apertures and Products Thereof
Patent: 5,403,685 →
Application: 07/954,505 →
Method for Fabricating a Self-Aligned Multi-Level Interconnect
Patent: 5,439,848 →
Application: 07/997,730 →
Method for Profile Control of Selective Metallization
Patent: 5,429,987 →
Application: 08/008,745 →
Pin-Hole Patch Method for Implanted Dielectric Layer
Patent: 5,278,077 →
Application: 08/028,832 →
Implantation of Nucleating Species for Selective Metallization and Products Thereof
Patent: 5,654,245 →
Application: 08/036,049 →
Bicmos Soi Structure Having Vertical Bjt and Method of Fabricating Same
Patent: 5,430,318 →
Application: 08/076,569 →
Non-Aqueous Electrolyte Secondary Battery and Its Production Method
Patent: 5,395,711 →
Application: 08/097,714 →
Method for Forming Gex Sil-X/Si/SIO2 Heterostructure Using Ge Implant
Patent: 5,792,679 →
Application: 08/113,995 →
Silylated Photoresist Layer and Planarizing Method
Patent: 5,486,424 →
Application: 08/191,701 →
System and Method for Analyzing Coded Transmission Sent to Mobile Message Receivers
Patent: 5,537,100 →
Application: 08/223,706 →
Ge-Si Soi Mos Transistor and Method of Fabricating Same
Patent: 5,726,459 →
Application: 08/258,518 →
Nitridation of Simox Buried Oxide
Patent: 5,468,657 →
Application: 08/261,443 →
Shallow Simox Processing Method Using Molecular Ion Implantation
Patent: 5,436,175 →
Application: 08/281,821 →
Methods and Equipment for Anisotropic, Patterned Conversion of Copper into Selectively Removable Compounds and for Removal of Same
Patent: 5,736,002 →
Application: 08/293,821 →
Graded Implantation of Oxygen and/or Nitrogen Constituents to Define Buried Isolation Region in Semiconductor Devices
Patent: 5,514,897 →
Application: 08/337,280 →
Semiconductor with Implanted Dielectric Layer Having Patched Pin-Holes
Patent: 5,608,252 →
Application: 08/357,077 →
Method of Forming a Pattern of Silylated Planarizing Photoresist
Patent: 5,545,512 →
Application: 08/437,559 →
Receiving Method and Apparatus for Use in a Spread-Spectrum Communication System
Patent: 5,671,221 →
Application: 08/490,193 →
Power Detector Using a Constant Quiescent Voltage Divider
Patent: 5,675,245 →
Application: 08/529,625 →
Radio Transceiver with Impedance Matched Test Port
Patent: 5,710,984 →
Application: 08/546,175 →
System and Method of Measuring a Battery Lifetime
Patent: 5,684,404 →
Application: 08/559,999 →
Shared Base Stations for Voice and Data Cellular Telecommunications and Method
Patent: 5,721,762 →
Application: 08/579,452 →
Battery Transposition System and Method
Patent: 5,712,553 →
Application: 08/586,245 →
System and Method for Correcting Burst Errors in Digital Information
Patent: 5,721,744 →
Application: 08/604,117 →
Method of Making Mos Transistor with Controlled Shallow Source/Drain Junction
Patent: 5,672,530 →
Application: 08/616,561 →
System and Method for Determining a Mobile Station Home Network Search Rate
Patent: 5,839,069 →
Application: 08/630,130 →
Method for Preventing Oxidation in the Formation of a via in an Integrated Circuit
Patent: 5,970,373 →
Application: 08/644,190 →
Method of Forming Polycrystalline Semiconductor Film from Amorphous Deposit by Modulating Crystallization with a Combination of Pre-Annealing and Ion Implantation
Patent: 6,383,899 →
Application: 08/653,258 →
Method for Forming a Multi-Level Reticle
Patent: 5,914,202 →
Application: 08/660,870 →
Multiple Exposure Masking System for Forming Multi-Level Resist Profiles
Patent: 5,753,417 →
Application: 08/665,013 →
Method for Transferring a Multi-Level Photoresist Pattern
Patent: 6,043,164 →
Application: 08/665,014 →
Hard Mask Method for Transferring a Multi-Level Photoresist Pattern
Patent: 5,821,169 →
Application: 08/692,379 →
System and Method for Conserving Battery Power in a Mobile Station Searching to Select a Serving Cell
Patent: 5,794,146 →
Application: 08/696,457 →
Raised Source/Drain Mos Transistor with Covered Epitaxial Notches and Fabrication Method
Patent: 5,677,214 →
Application: 08/708,683 →
Oxidized Diffusion Barrier Surface for the Adherence of Copper and Method for Same
Patent: 5,913,144 →
Application: 08/717,267 →
Copper Adhesion to a Diffusion Barrier Surface and Method for Same
Patent: 5,909,637 →
Application: 08/717,315 →
Method for a Chemical Vapor Deposition of Copper on an Ion Prepared Conductive Surface
Patent: 5,918,150 →
Application: 08/729,567 →
Differential Copper Deposition on Integrated Circuit Surfaces and Method for Same
Patent: 5,851,367 →
Application: 08/731,258 →
Method of Using Water Vapor to Increase the Conductivity of Copper Deposited with Cu(Hfac)Tmvs
Patent: 5,744,192 →
Application: 08/745,562 →
Raised Silicided Source/Drain Electrode Formation with Reduced Substrate Silicon Consumption
Patent: 5,830,775 →
Application: 08/756,782 →
Retractable Antenna Connector Assembly System and Method
Patent: 5,812,098 →
Application: 08/756,783 →
Method of Forming Transistor Electrodes Frosm Directionally Deposited Silicide
Patent: 5,814,537 →
Application: 08/768,647 →
Precursor with (Methoxy)(Methyl)Silylolefin Ligands to Deposit Copper and Method for Same
Patent: 6,090,960 →
Application: 08/779,640 →
Silylated Photo-Resist Layer and Planarizing Method
Patent: 5,756,256 →
Application: 08/784,038 →
Precursor with (Alkyloxy)(Alkyl)-Silylolefin Ligand to Deposit Copper
Patent: 5,767,301 →
Application: 08/786,546 →
One Transistor Ferroelectric Memory Cell and Method of Making the Same
Patent: 5,731,608 →
Application: 08/812,579 →
Method for Forming Polcrystalline Silicon from the Crystallization of Microcrystalline Silicon
Patent: 5,827,773 →
Application: 08/812,580 →
System and Method for Intuitively Indicating Signal Quality in a Wireless Digital Communications Network
Patent: 6,243,568 →
Application: 08/821,997 →
Shallow Junction Ferroelectric Memory Cell Having a Laterally Extending P-N Junction and Method of Making the Same
Patent: 6,018,171 →
Application: 08/834,499 →
Mos Transistor with Controlled Shallow Source/Drain Junction, Source/ Drain Strap Portions, and Source/Drain Electrodes on Field Insulation Layers
Patent: 5,932,913 →
Application: 08/847,916 →
System and Method of Selectively Cleaning Copper Substrate Surfaces, in-Situ, to Remove Copper Oxides
Patent: 5,939,334 →
Application: 08/861,808 →
Shallow Junction Ferroelectric Memory Cell and Method of Making the Same
Patent: 5,942,776 →
Application: 08/869,534 →
Two Transistor Ferroelectric Memory Cell
Patent: 5,932,904 →
Application: 08/870,161 →
Method of Making Ferroelectric Memory Cell for Vlsi Ram
Patent: 6,048,738 →
Application: 08/870,375 →
Thin-Film Transistor Polycrystalline Thin Film Formation by Nickel- Induced, Rapid Thermal Annealing Method
Patent: 6,066,547 →
Application: 08/879,386 →
Selective Silicide Thin-Film Transistor and Method for Same
Patent: 5,940,693 →
Application: 08/893,285 →
Low Resistance Contact Between Integrated Circuit Metal Levels and Method for Same
Patent: 5,904,565 →
Application: 08/896,114 →
Single Transistor Ferroelectric Memory Cell with Asymmetrical Ferroelectric Polarization and Method of Making the Same
Patent: 5,962,884 →
Application: 08/905,380 →
Dual Clock Power Conservation System and Method for Timing Synchronous Communications
Patent: 6,044,282 →
Application: 08/911,629 →
A Method for Fabricating Asymmetric Channel Doped Structure
Patent: 5,891,782 →
Application: 08/918,678 →
Method of Making Gate and Source Lines in Tft Lcd Panels Using Pure Aluminum Metal
Patent: 5,994,156 →
Application: 08/928,600 →
Rapid Thermal Annealing with Absorptive Layers for Thin Film Transistors on Transparent Substrates
Patent: 5,950,078 →
Application: 08/934,347 →
Adaptive Step-Size Motion Estimation Based on Statistical Sum of Absolute Differences
Patent: 6,014,181 →
Application: 08/949,303 →
System and Method of Additive Interpolaton for Affine Transformations
Patent: 6,028,969 →
Application: 08/958,137 →
System and Method for Peeling a Polarized Film
Patent: 5,891,297 →
Application: 08/960,011 →
Method of Manufacture of Single Transistor Ferroelectric Memory Cell Using Chemical-Mechanical Polishing
Patent: 5,907,762 →
Application: 08/984,789 →
Locos Mos Device for Esd Protection
Patent: 5,910,673 →
Application: 08/984,801 →
Low Temperature System and Method for Cvd Copper Removal
Patent: 5,897,379 →
Application: 08/995,112 →
C-Axis Oriented Thin Film Ferroelectric Transistor Memory Cell and Method of Making the Same
Patent: 6,011,285 →
Application: 09/002,364 →
Method of Making Metal Gate Sub-Micron Mos Transistor
Patent: 6,274,421 →
Application: 09/004,991 →
Multi-Level Photoresist Profile Method
Patent: 5,906,910 →
Application: 09/008,257 →
Multi-Level Reticle System and Method for Forming Multi-Level Resist Profiles
Patent: 5,936,707 →
Application: 09/008,362 →
Nitride Overhang Structures for the Silicidation of Transistor Electrodes with Shallow Junction
Patent: 5,989,965 →
Application: 09/023,032 →
Method of Maiking Low-K Fluorinated Amorphous Carbon Dielectric
Patent: 5,900,290 →
Application: 09/023,382 →
Partial Silicidation Method to Form Shallow Source/Drain Junctions
Patent: 6,071,782 →
Application: 09/023,383 →
Fabrication of a Planar Mosfet with Raised Source/Drain by Chemical Mechanical Polishing and Nitride Replacement
Patent: 6,133,106 →
Application: 09/028,157 →
Method of Forming Fully Depleted Simox Cmos Having Electrostatic Discharge Protection
Patent: 6,114,197 →
Application: 09/031,143 →
Trench Isolation Structure and Method for Same
Patent: 6,169,011 →
Application: 09/047,038 →
Method of Forming Nitrogen Implanted Ultrathin Gate Oxide for Dual Gate Cmos Devices
Patent: 6,184,110 →
Application: 09/071,234 →
A Method of Forming an Ultra-Thin Soi Electrostatic Discharge Protection Device
Patent: 6,080,612 →
Application: 09/082,084 →
Stress-Loaded Film and Method for Same
Patent: 6,184,157 →
Application: 09/088,456 →
Method for Manufacturing a Cmos Self- Aligned Strapped Interconnection
Patent: 5,915,199 →
Application: 09/090,802 →
Selected Site, Metal-Induced, Continuous Crystallization Method
Patent: 6,228,693 →
Application: 09/092,831 →
Adhesion Promotion Method for Cvd Copper Metallization in Ic Applications
Patent: 6,355,562 →
Application: 09/108,260 →
Double Sidewall Raised Silicided Source/Drain Cmos Transistor
Patent: 6,368,960 →
Application: 09/113,667 →
Single Crystal Tft from Continuous Transition Metal Delivery Method
Patent: 6,346,437 →
Application: 09/118,307 →
Enhanced Cvd Copper Adhesion by Two-Step Deposition Process
Patent: 5,948,467 →
Application: 09/122,346 →
Electrostatic Discharge Protection for Salicided Devices and Method of Making Same
Patent: 6,211,001 →
Application: 09/122,494 →
Differential Copper Deposition on Integrated Circuit Surfaces
Patent: 6,002,176 →
Application: 09/135,376 →
Polycrystalline Silicon from Crystallization of Microcrystalline Silicon and Method for Same
Patent: 5,959,314 →
Application: 09/135,393 →
In-Situ Method of Cleaning a Metal-Organic Chemical Vapor Deposition Chamber
Patent: 6,284,052 →
Application: 09/136,881 →
Publication: US 2001/0009154
Low Resistance Contact Between Circuit Metal Levels
Patent: 6,023,102 →
Application: 09/169,084 →
Ferroelectric Nonvolatile Transistor and Method of Making Same
Patent: 6,048,740 →
Application: 09/187,238 →
Adhesion Promotion Method for Electro-Chemical Copper Metallization in Ic Applications
Patent: 6,284,652 →
Application: 09/188,020 →
Asymmetric Mos Channel Structure with Drain Extension and Method for Same
Patent: 6,291,325 →
Application: 09/195,392 →
Substituted Phenylethylene Precursor and Synthesis Method
Patent: 6,245,261 →
Application: 09/210,099 →
Substituted Ethylene Precursor and Synthesis Method
Patent: 5,994,571 →
Application: 09/215,921 →
Semiconductor Wafer with Removed Cvd Copper
Patent: 6,020,639 →
Application: 09/223,927 →
Copper Adhered to a Diffusion Barrier Surface
Patent: 6,218,734 →
Application: 09/247,650 →
Chemically Active Slurry for the Polishing of Noble Metals and Method for Same
Patent: 6,290,736 →
Application: 09/247,655 →
Laser Annealed Microcrystalline Film and Method for Same
Patent: 6,329,270 →
Application: 09/248,629 →
Method for Fabricating a Locos Mos Device for Esd Protection
Patent: 6,140,189 →
Application: 09/248,630 →
Method of Optimizing Crystal Grain Size in Polycrystalline Silicon Films
Patent: 6,169,013 →
Application: 09/248,631 →
Cmos Self-Aligned Strapped Interconnect
Patent: 6,388,296 →
Application: 09/257,217 →
Iridium Conductive Electrode/Barrier Structure and Method for Same
Application: 09/263,595 →
Publication: US 2001/0013637
Iridium Composite Barrier Structure and Method for Same
Patent: 6,236,113 →
Application: 09/263,970 →
Method for Modification of Polishing Pattern Dependence in Chemical Mechanical Polishing
Application: 09/270,606 →
Publication: US 2001/0044209
System for Selectively Cleaning Copper Substrate Surfaces, in-Situ, to Remove Copper Oxides
Patent: 6,281,589 →
Application: 09/270,901 →
Edger
Patent: 360,563 →
Application: 29/025,917 →
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. Oct 4, 1991
From: SOOD, PREM LAL
To: SHARP MICROELECTRONICS TECHNOLOGY, INC.
Reel/Frame 005875/0737 →
Assignment of Assignors Interest. Jul 28, 1992
From: VIDUSEK, DAVID A.
To: SHARP MICROELECTRONICS TECHNOLOGY, INC.
Reel/Frame 006234/0255 →
Each Assignee an Undivided 1/2 Share in the Entire Right. Jan 25, 1993
From: ALLEN, GREGORY L.
To: SHARP MICROELECTRONICS TECHNOLOGY, INC.; SHARP KABUSHIKI KAISHA
Reel/Frame 006398/0873 →
Assignment of Assignors Interest. Mar 10, 1993
From: NAKATO, TATSUO
To: SHARP MICROELECTRONICS TECHNOLOGY, INC.; SHARP KABUSHIKI KAISHA
Reel/Frame 006468/0057 →
Assignment of Assignor's Interest Mar 12, 1993
From: HSU, SHENG T.; POLLACHEK, ROBERT G.
To: SHARP MICROELECTRONICS TECHNOLOGY, INC.; SHARP KABUSHIKI KAISHA
Reel/Frame 006602/0347 →
Assignment of Assignor's Interest May 21, 1993
From: ALLEN, GREGORY LEE
To: SHARP MICROELECTRONICS TECHNOLOGY, INC.
Reel/Frame 006556/0611 →
Assignment of Assignor's Interest Jun 7, 1993
From: VIDUSEK, DAVID ARTHUR; TABUCHI, HIROKI
To: SHARP MICROELECTRONICS TECHNOLOGY, INC.; SHARP KABUSHIKI KAISHA
Reel/Frame 006576/0394 →
Assignment of Assignor's Interest Jun 14, 1993
From: HSU, SHENG T.
To: SHARP MICROELECTRONICS TECH. INC.
Reel/Frame 006586/0718 →
Corrected Assignment Aug 6, 1993
From: SHARP MICROELECTRONICS TECHNOLOGY, INC.
To: SHARP KABUSHIKI KAISHA
Reel/Frame 006629/0096 →
Assignment of Assignor's Interest Aug 30, 1993
From: NAKATO, TATSUO
To: SHARP MICROELECTRONICS TECHNOLOGY, INC.
Reel/Frame 006685/0720 →
Assignment of Assignor's Interest Dec 15, 1993
From: SHARP MICROELECTRONICS TECHNOLOGY, INC.
To: SHARP KABUSHIKI KAISHA
Reel/Frame 006800/0253 →
Assignment of Assignor's Interest Dec 27, 1993
From: HSU, SHENG TENG
To: SHARP MICROELECTRONICS TECHNOLOGY, INC.
Reel/Frame 006812/0377 →
Assignment of Assignor's Interest Apr 6, 1994
From: HALLBERG, BRYAN S.
To: SHARP MICROELECTRONICS TECHNOLOGY, INC.
Reel/Frame 006953/0593 →
Assignment of Assignor's Interest Jun 17, 1994
From: HSU, SHENG TENG
To: SHARP MICROELECTRONICS TECHNOLOGY, INC.
Reel/Frame 007043/0325 →
Assignment of Assignor's Interest Jul 27, 1994
From: NAKATO, TATSUO; MEYYAPPAN, NARAYANAN
To: SHARP MICROELECTRONICS TECHNOLOGY, INC.
Reel/Frame 007098/0076 →
Assignment of Assignor's Interest Aug 22, 1994
From: ALLEN, LYNN RENEE; GRANT, JOHN MARTIN
To: SHARP MICROELECTRONICS TECHNOLOGY, INC.; SHARP KABUSHIKI KAISHA
Reel/Frame 007138/0006 →
Assignment of Assignor's Interest Nov 7, 1994
From: SHARP MICROELECTRONICS TECHNOLOGY, INC.
To: SHARP KABUSHIKI KAISHA
Reel/Frame 007199/0959 →
Assignment of Assignor's Interest Nov 7, 1994
From: SHARP MICROELECTRONICS TECHNOLOGY, INC.
To: SHARP KABUSHIKI KAISHA
Reel/Frame 007196/0371 →
Assignment of Assignor's Interest Nov 8, 1994
From: SHARP MICROELECTRONICS TECHNOLOGY, INC.
To: SHARP KABUSHIKI KAISHA
Reel/Frame 007200/0842 →
Assignment of Assignor's Interest Nov 21, 1994
From: TAHARA, KENSUKE; ISHIKAWA, HIDEKI; IWASAKI, FUMIHARU; YAHAGI, SEIJI
To: SEIKO INSTRUMENTS INC.; SEIKO ELECTRONIC COMPONENTS LTD.
Reel/Frame 007216/0556 →
Assignment of an Undivided Half Interest to Assignee. Feb 21, 1995
From: SHARP MICROELECTRONICS TECHNOLOGY, INC.
To: SHARP KABUSHIKI KAISHA
Reel/Frame 007343/0571 →
Assignment of Assignor's Interest Mar 17, 1995
From: SHARP MICROELECTRONICS TECHNOLOGY, INC.
To: SHARP KABUSHIKI KAISHA
Reel/Frame 007397/0918 →
Assignment of Assignor's Interest May 4, 1995
From: SHARP MICROELECTRONICS TECHNOLOGY, INC.
To: SHARP KABUSHIKI KAISHA
Reel/Frame 007467/0606 →
Assignment of Assignor's Interest Jun 14, 1995
From: YANG, JIN
To: SHARP MICROELECTRONICS TECHNOLOGY, INC.
Reel/Frame 007611/0278 →
Assignment of an Undivided Half Interest to Assignee Jul 17, 1995
From: SHARP MICROELECTRONICS TECHNOLOGY, INC.
To: SHARP KABUSHIKI KAISHA
Reel/Frame 007573/0012 →