Patent Assignment
Reel/Frame 074577/0935
Merger and Change of Name
Recorded: 2026-01-27
Pages: 11
Assignors
RENESAS ELECTRONICS AMERICA INC.
Executed: 2019-12-10
INTEGRATED DEVICE TECHNOLOGY, INC.
Executed: 2019-12-10
Assignee
RENESAS ELECTRONICS AMERICA INC.
6024 SILVER CREEK VALLEY ROAD, SAN JOSE, CALIFORNIA, 95138
Covered Properties
(122)
Phase-Locked Loop Circuits with Current Mode Loop Filters
Method and Apparatus for Pre-Clocking
Method and Apparatus for Pre-Clocking
Patent:
7,629,816 →
Application:
11/872,027 →
Simple Technique for Reduction of Gain in a Voltage Controlled Oscillator
Digitally Compensated Highly Stable Holdover Clock Generation Techniques Using Adaptive Filtering
High Speed Hybrid Structure Counter Having Synchronous Timing and Asynchronous Counter Cells
Voltage-To-Current Converter
Auto-Adaptive Digital Phase-Locked Loop for Large Frequency Multiplication Factors
Phase Difference Detector Having Concurrent Fine and Coarse Capabilities
Phase Step Clock Generator
Patent:
7,737,739 →
Application:
11/955,340 →
Phase-Locked Loop
Clock Circuit for Reducing Long Term Jitter
Patent:
7,816,959 →
Application:
12/391,105 →
Micro-Electromechanical Devices Having Variable Capacitors Therein That Compensate for Temperature-Induced Frequency Drift in Acoustic Resonators
Multiple Frequency Synchronized Phase Clock Generator
Methods and Apparatuses for Incremental Bandwidth Changes Responsive to Frequency Changes of a Phase-Locked Loop
Method and Apparatus for Adjusting Pll and/or Dll Timing Offsets
Patent:
7,956,693 →
Application:
11/739,546 →
Charge Pump Linearization Technique for Delta-Sigma Fractional-N Synthesizers
Non-Linear Crystal Oscillator Capacitive Load Circuits
Patent:
7,990,226 →
Application:
12/463,749 →
Method for Binary Clock and Data Recovery for Fast Acquisition and Small Tracking Error
Automated Clock Relationship Detection
Digital Spread Spectrum Method Based on Precise Phase Delta-Sigma Algorithm
Holdover Circuit for Phase-Lock Loop
Patent:
8,018,289 →
Application:
12/544,201 →
Apparatus and Method for Detecting the Loss of an Input Clock Signal for a Phase-Locked Loop
Asynchronous Biphase Mark Signal Receivers and Methods of Operating Same
Patent:
8,023,594 →
Application:
12/171,612 →
Synchronous De-Skew with Programmable Latency for Multi-Lane High Speed Serial Interface
Overclocking with Phase Selection
High Frequency Fractional-N Divider
Method and Apparatus for Frequency Compensation for Multi-Band Vco
Patent:
8,093,957 →
Application:
12/561,166 →
Clock, Frequency Reference, and Other Reference Signal Generator with a Controlled Quality Factor
Integrated Circuit Systems Having Processor-Controlled Clock Signal Generators Therein That Support Efficient Power Management
Thin-Film Bulk Acoustic Resonators Having Perforated Resonator Body Supports That Enhance Quality Factor
Patent:
8,106,724 →
Application:
12/508,257 →
Linear Monotonic Delay Chain Circuit
Clock, Frequency Reference, and Other Reference Signal Generator with Frequency Stability Over Temperature Variation
Method and Apparatus for Auto-Frequency Calibration for Multi-Band Vco
Patent:
8,138,845 →
Application:
12/561,039 →
Spread Spectrum Clock Generation Technique for Imaging Applications
Patent:
8,164,367 →
Application:
12/354,453 →
Method of Processing Signal Data with Corrected Clock Phase Offset
Method and Apparatus for Fast Pll Initialization
Patent:
8,265,219 →
Application:
11/428,071 →
Methods of Forming Microdevice Substrates Using Double-Sided Alignment Techniques
Patent:
8,283,256 →
Application:
13/034,004 →
Push-Pull Spread Spectrum Clock Signal Generator
Patent:
8,284,816 →
Application:
12/476,177 →
Method and Apparatus for Fail-Safe Start-Up Circuit for Subthreshold Current Sources
Patent:
8,316,245 →
Application:
12/333,149 →
Thin-Film Bulk Acoustic Resonators Having Multi-Axis Acoustic Wave Propagation Therein
Patent:
8,368,487 →
Application:
12/713,940 →
Methods of Forming Micro-Electromechanical Resonators Using Passive Compensation Techniques
Patent:
8,501,515 →
Application:
13/035,148 →
Multi-Band Clock Generator with Adaptive Frequency Calibration and Enhanced Frequency Locking
Patent:
8,509,372 →
Application:
12/626,256 →
Method and Apparatus for Implementation of Pll Minimum Frequency via Voltage Comparison
Patent:
8,513,992 →
Application:
12/879,995 →
Third Overtone Crystal-Based Oscillators Having Tunable All-Pass Rc Filters Therein
Patent:
8,519,800 →
Application:
13/247,566 →
Reconfigurable Divider Circuits with Hybrid Structure
Patent:
8,542,040 →
Application:
13/285,103 →
Frequency Synthesizers with Dynamic Calibration Intervals
Patent:
8,552,804 →
Application:
13/249,659 →
Fractional-N Dividers Having Divider Modulation Circuits Therein with Segmented Accumulators
Patent:
8,559,587 →
Application:
13/425,761 →
Microelectromechanical Resonators with Thermally-Actuated Frequency Tuning Beams
Patent:
8,633,635 →
Application:
13/174,082 →
Methods of Testing Packaged Thin-Film Piezoelectric-on-Semiconductor Microelectromechanical Resonators Having Hermetic Seals
Patent:
8,638,178 →
Application:
13/407,484 →
Method and Apparatus for Glitch-Free Switching of Multiple Phase Clock
Patent:
8,680,910 →
Application:
12/640,750 →
Periodic Signal Generators Having Microelectromechanical Resonators Therein That Support Surface Wave and Bulk Acoustic Wave Modes of Operation with Different Temperature Coefficients of Frequency
Patent:
8,680,931 →
Application:
13/435,817 →
Ac Coupled Clock Receiver with Common-Mode Noise Rejection
Patent:
8,693,557 →
Application:
12/497,485 →
Systems, Apparatuses and Methods for Dynamic Voltage and Frequency Control of Components Used in a Computer System
Periodic Signal Generators Having Microelectromechanical Resonators Therein That Support Generation of High Frequency Low-Tcf Difference Signals
Patent:
8,742,854 →
Application:
13/186,332 →
Integrated Circuit Devices Using Analog Dividers
Patent:
8,754,719 →
Application:
13/334,535 →
Methods of Forming Micro-Electromechanical Resonators Having Passive Temperature Compensation Regions Therein
Patent:
8,785,229 →
Application:
13/898,999 →
Microelectromechanical-Based Oscillators Having Adjustable Gain Amplifiers Therein That Support Q-Factor Control
Patent:
8,803,622 →
Application:
13/629,732 →
Multiple Time Domain Synchronizer Circuits
Patent:
8,826,057 →
Application:
13/538,643 →
Current Mode Logic Circuits with Automatic Sink Current Adjustment
Patent:
8,847,628 →
Application:
13/631,933 →
Clock Distribution Systems for Low Power Applications
Patent:
8,854,086 →
Application:
13/795,828 →
Timing Controllers Having Partitioned Pipelined Delay Chains Therein
Patent:
8,943,242 →
Application:
13/436,324 →
High Frequency Precision Oscillators Having Stable Temperature Characteristics
Patent:
8,981,856 →
Application:
14/015,837 →
Packaged Mems-Based Oscillator Circuits That Support Frequency Margining and Methods of Operating Same
Patent:
9,000,853 →
Application:
13/849,999 →
Clock Generation Circuits Using Jitter Attenuation Control Circuits with Dynamic Range Shifting
Patent:
9,065,459 →
Application:
13/829,202 →
Microelectromechanical Resonators Having Offset [100] and [110] Crystal Orientations
Patent:
9,090,451 →
Application:
13/837,854 →
Self-Adaptive Multi-Modulus Dividers Containing DIV2/3 Cells Therein
Patent:
9,118,333 →
Application:
14/013,599 →
Digital Filter for Phase-Locked Loop Integrated Circuits
Patent:
9,236,871 →
Application:
14/460,653 →
Fractional Divider Based Phase Locked Loops with Digital Noise Cancellation
Patent:
9,236,873 →
Application:
14/573,146 →
Methods of Packet-Based Synchronization in Non-Stationary Network Environments
Patent:
9,236,967 →
Application:
13/799,086 →
Process Compensated Delay
Patent:
9,264,027 →
Application:
14/190,890 →
Half-Integer Frequency Dividers That Support 50% Duty Cycle Signal Generation
Patent:
9,270,280 →
Application:
14/136,012 →
Method and Apparatus for Fast Frequency Acquisition in Pll System
Patent:
9,362,924 →
Application:
14/794,770 →
Low-Spurious Fractional N-Frequency Divider and Method of Use
Patent:
9,362,928 →
Application:
14/794,782 →
Fractional Reference-Injection Pll
Patent:
9,369,139 →
Application:
14/622,851 →
Dual-Coupled Phase-Locked Loops for Clock and Packet-Based Synchronization
Patent:
9,369,270 →
Application:
14/212,598 →
Low Voltage Differential Signaling (Lvds) Driver with Differential Output Signal Amplitude Regulation
Patent:
9,407,268 →
Application:
14/700,034 →
Monolithic Composite Resonator Devices with Reduced Sensitivity to Acceleration and Vibration
Patent:
9,431,955 →
Application:
14/985,689 →
Methods of Performing Time-of-Day Synchronization in Packet Processing Networks
Patent:
9,444,566 →
Application:
14/200,619 →
Controlling Operation of a Timing Device Using an Otp Nvm to Store Timing Device Configurations in a Ram
Patent:
9,455,045 →
Application:
14/691,472 →
Self-Calibrating Fractional Divider Circuits
Patent:
9,479,177 →
Application:
14/575,212 →
Methods and Apparatus for Synchronizing Operations Using Separate Asynchronous Signals
Patent:
9,479,182 →
Application:
14/975,388 →
Low Power Driver with Programmable Output Impedance
Integrated Circuits Having Multiple Digitally-Controlled Oscillators (Dcos) Therein That Are Slaved to the Same Loop Filter
Patent:
9,490,828 →
Application:
14/884,324 →
Initiating Operation of a Timing Device Using a Read Only Memory (Rom) or a One Time Programmable Non Volatile Memory (Otp Nvm)
Integrated Circuit Devices Having Oscillator Circuits Therein That Support Fixed Frequency Generation Over Process-Voltage-Temperature (Pvt) Variations
Patent:
9,503,059 →
Application:
14/871,319 →
Temperature Detection Method and Device with Improved Accuracy and Conversion Time
Multi-Stage Frequency Dividers Having Duty Cycle Correction Circuits Therein
Patent:
9,543,960 →
Application:
14/966,913 →
Crystal-Less Jitter Attenuator
Patent:
9,553,570 →
Application:
14/566,571 →
Methods and Systems for Analog-to-Digital Conversion (Adc) Using an Ultra Small Capacitor Array with Full Range and Sub-Range Modes
Patent:
9,553,602 →
Application:
15/076,327 →
Dual Mode Clock Using a Common Resonator and Associated Method of Use
Patent:
9,581,973 →
Application:
15/083,831 →
High-Speed Programmable Frequency Divider with 50% Output Duty Cycle
Patent:
9,590,637 →
Application:
14/839,817 →
Methods and Apparatus for Transmitting Data Over a Clock Signal
Patent:
9,628,255 →
Application:
14/975,226 →
Calibration Method and Apparatus for Phase Locked Loop Circuit
Patent:
9,654,121 →
Application:
15/169,997 →
Fractional Divider Using a Calibrated Digital-to-Time Converter
Patent:
9,678,481 →
Application:
15/185,378 →
Packaged Oscillators with Built-in Self-Test Circuits That Support Resonator Testing with Reduced Pin Count
Patent:
9,791,503 →
Application:
14/871,411 →
Adaptive High-Speed Current-Steering Logic (Hcsl) Drivers
Patent:
9,838,016 →
Application:
15/050,646 →
Frequency Synthesizer with Microcode Control
Patent:
9,847,869 →
Application:
15/210,204 →
Phase Locked Loop (Pll) Timing Device Evaluation System and Method for Evaluating Pll Timing Devices
Patent:
9,852,039 →
Application:
15/015,094 →
Buffer with Programmable Input/Output Phase Relationship
Patent:
9,859,901 →
Application:
15/064,369 →
Fractional Divider Using a Calibrated Digital-to-Time Converter
Timing Device Having Multi-Purpose Pin with Proactive Function
Patent:
9,954,516 →
Application:
14/830,698 →
Bulk Acoustic Wave Resonator Based Fractional Frequency Synthesizer and Method of Use
Patent:
9,954,541 →
Application:
15/084,067 →
Pulse Width Modulation (Pwm) to Align Clocks Across Multiple Separated Cards Within a Communication System
Patent:
10,075,284 →
Application:
15/364,602 →
Frequency Synthesizer with Tunable Accuracy
Process Compensated Delay
Patent:
10,110,209 →
Application:
14/675,369 →
Arbitrary Delay Buffer
Separate Clock Synchronous Architecture
Wirelessly Synchronized Clock Networks
Frequency Divider with Selectable Frequency and Duty Cycle
Hitless Re-Arrangements in Coupled Digital Phase-Locked Loops
Methods of Estimating Frequency Skew in Networks Using Timestamped Packets
Patent:
10,374,786 →
Application:
14/992,486 →
Time Slotted Bus System for Multiple Coupled Digital Phase-Locked Loops
Frequency Synthesizer with Tunable Accuracy
Use of Ring Oscillators for Multi-Stop Time Measurements
Time Slotted Bus System for Multiple Coupled Digital Phase-Locked Loops
Hitless Re-Arrangements in Coupled Digital Phase-Locked Loops
Wirelessly Synchronized Clock Networks
Minimizing Timestamp Error in Ptp Systems
Apparatus and Methods for Automatic Time Measurements
Fast Protection Switching in Distributed Systems
Zero Offset Clock Distribution
Related Assignments
(22)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Dec 21, 2005
From: FRANK, INGOLF; MCRAE, DUNCAN
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 017407/0955 →
Assignment of Assignor's Interest
Mar 28, 2006
From: ROETHIG, WOLFGANG
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 017376/0252 →
Assignment of Assignor's Interest
Apr 3, 2006
From: YAN, GANG
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 017428/0726 →
Assignment of Assignor's Interest
Nov 14, 2006
From: YI, LI
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 018593/0419 →
Assignment of Assignor's Interest
Apr 11, 2007
From: ISIK, TACETTIN
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 019148/0301 →
Assignment of Assignor's Interest
Apr 24, 2007
From: HRONIK, STANLEY, MR.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 019205/0115 →
Assignment of Assignor's Interest
Dec 12, 2007
From: BI, HAN
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 020237/0310 →
Assignment of Assignor's Interest
Dec 17, 2007
From: SHAO, ZHUYAN; QIAO, JUAN
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 020314/0288 →
Assignment of Assignor's Interest
Dec 18, 2007
From: BI, HAN
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 020262/0415 →
Assignment of Assignor's Interest
Jan 2, 2008
From: LIU, XIN; ZHANG, LIANG; WANG, YONG
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 020306/0329 →
Assignment of Assignor's Interest
Feb 20, 2008
From: LIU, XIN; ZHANG, LIANG; WANG, YONG
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 020537/0571 →
Assignment of Assignor's Interest
Mar 20, 2008
From: WANG, YANBO; ZHANG, XIAOQIAN; ZHAI, SHUBING
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 020740/0614 →
Assignment of Assignor's Interest
Jul 27, 2008
From: LI, YI; CHI, JI FU
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 021296/0680 →
Assignment of Assignor's Interest
Feb 23, 2009
From: ISIK, TACETTIN
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 022298/0179 →
Assignment of Assignor's Interest
Mar 16, 2009
From: WANG, YE; BHUGRA, HARMEET
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 022402/0041 →
Assignment of Assignor's Interest
May 12, 2009
From: AYCOCK, STEPHEN E.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 022669/0755 →
Assignment of Assignor's Interest
Jun 17, 2009
From: SONG, ANFEI
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 022839/0909 →
Assignment of Assignor's Interest
Jun 29, 2009
From: YANG, ZHENYU; LIU, TIANWEI
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 022888/0161 →
Security Agreement
Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
Release of Security Interest
Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION
Reel/Frame 048746/0001 →
Assignment of Assignor's Interest
Aug 27, 2026
From: RENESAS ELECTRONICS AMERICA INC.
To: SITIME CORPORATION
Reel/Frame 075811/0310 →
Assignment of Assignor's Interest
Aug 27, 2026
From: RENESAS ELECTRONICS AMERICA INC.
To: SITIME CORPORATION
Reel/Frame 075811/0217 →