IP Library › Assignment 010255/0405
Patent Assignment
Reel/Frame 010255/0405

Assignment of Assignor's Interest

Recorded: 1999-09-11 Pages: 31
Assignor
HARRIS CORPORATION
Executed: 1999-08-13
Assignee
INTERSIL CORPORATION
2401 PALM BAY ROAD, N.E., PALM BAY, FLORIDA, 32905
Covered Properties (251)
Thyristor Cathode and Transistor Emitter Structures with Insulator Islands
Patent: 4,581,626 →
Application: 06/028,576 →
Solid State Relay
Patent: 4,268,843 →
Application: 06/112,397 →
Composite Conductive Structures in Integrated Circuits and Method of Making Same
Patent: 4,263,058 →
Application: 06/115,069 →
Latching Transistor
Patent: 4,356,503 →
Application: 06/125,413 →
Method and Apparatus for Thermo-Compression Diffusion Bonding
Patent: 4,252,263 →
Application: 06/139,177 →
Vertical Channel Field Effect Transistor
Patent: 4,343,015 →
Application: 06/149,936 →
High Breakdown Voltage Semiconductor Device
Patent: 4,374,389 →
Application: 06/159,813 →
Method of Making Low Resistance Contacts in Semiconductor Devices by Ion Induced Silicides
Patent: 4,339,869 →
Application: 06/187,043 →
Method of Making Integrated Circuits
Patent: 4,333,964 →
Application: 06/187,430 →
Method of Making Integrated Circuits
Patent: 4,333,965 →
Application: 06/187,501 →
Integrated Circuit and Method of Making Same
Patent: 4,378,565 →
Application: 06/192,881 →
Use of Dispersed Solids as Fillers in Polymeric Materials to Provide Material for Semiconductor Junction Passivation
Patent: 4,331,970 →
Application: 06/201,143 →
Fiber Optic Coupler
Patent: 4,377,322 →
Application: 06/201,350 →
Thermal Stress Relieving Bimetallic Plate
Patent: 4,427,993 →
Application: 06/209,001 →
Integrated Circuit Incorporating Low Voltage and High Voltage Semiconductor Devices
Patent: 4,412,142 →
Application: 06/219,824 →
Transistor Having Improved Turn-Off Time and Second Breakdown Characteristics with Bi-Level Emitter Structure
Patent: 4,345,266 →
Application: 06/236,220 →
Method of Restoring Semiconductor Device Performance
Patent: 4,341,594 →
Application: 06/238,726 →
Alignment-Enhancing Feed-Through Conductors for Stackable Silicon-on- Sapphire Wafers
Patent: 4,394,712 →
Application: 06/244,854 →
Thin Film Binary Metallic Eutectics
Patent: 4,500,609 →
Application: 06/245,764 →
Method of Forming a Conductor Pattern Including Fine Conductor Runs on a Ceramic Substrate
Patent: 4,413,766 →
Application: 06/250,992 →
Process for X-Ray Microlithography Using Thin Film Eutectic Masks
Patent: 4,349,621 →
Application: 06/253,985 →
Blister-Free Direct Bonding of Metals to Ceramics and Metals
Patent: 4,409,278 →
Application: 06/254,840 →
Composite Circuit for Power Semiconductor Switching
Patent: 4,663,547 →
Application: 06/257,080 →
Simultaneously Doped Light-Emitting Diode
Application: 06/261,584 →
Irradiation Apparatus Utilizing Linear Radiation Sources
Patent: 4,415,955 →
Application: 06/276,137 →
Periodic Reverse Current Pulsing to Form Uniformly Sized Feed Through Conductors
Patent: 4,396,467 →
Application: 06/285,668 →
Method of Forming an Isolation Trench in a Semiconductor Substrate
Patent: 4,390,393 →
Application: 06/320,379 →
Method of Making Integrated Circuits Utilizing Ion Implantation and Selective Epitaxial Growth
Patent: 4,412,868 →
Application: 06/333,596 →
Bimodal Bus Accessing System
Patent: 4,439,856 →
Application: 06/351,820 →
Composite Conductive Structures and Method of Making Same
Patent: 4,429,011 →
Application: 06/362,682 →
Mosfet-Gated Bipolar Transistors and Thyristors with Both Turn-on and Turn-Off Capability Having Single-Polarity Gate Input Signal
Patent: 5,014,102 →
Application: 06/364,294 →
Dual Gate Cmos Transistor Circuits Having Reduced Electrode Capacitance
Patent: 4,468,574 →
Application: 06/374,586 →
Dynamic Shift Register Utilizing Cmos Dual Gate Transistors
Patent: 4,472,821 →
Application: 06/374,587 →
Insulating Film Having Electrically Conducting Portions
Patent: 4,803,528 →
Application: 06/380,284 →
Electrical Assembly Including a Conductor Pattern Bonded to a Non- Metallic Substrate and Method of Fabricating Such Assembly
Patent: 4,500,029 →
Application: 06/387,717 →
Method of Fabricating a Semiconductor Device with a Base Region Having a Deep Portion
Patent: 4,443,931 →
Application: 06/392,870 →
High Voltage Semiconductor Devices
Patent: 4,494,134 →
Application: 06/394,346 →
Semiconductor Devices Utilizing Eutectic Masks
Patent: 4,500,898 →
Application: 06/395,761 →
Method for Making Surface Acoustic Wave Devices
Patent: 4,414,243 →
Application: 06/395,778 →
System for Polynomial Division Self-Testing of Digital Networks
Patent: 4,498,172 →
Application: 06/402,161 →
Process for Manufacturing Insulated-Gate Semiconductor Devices with Integral Shorts
Patent: 4,417,385 →
Application: 06/406,731 →
Minimal Mask Process for Manufacturing Insulated-Gate Semiconductor Devices with Integral Shorts
Patent: 4,430,792 →
Application: 06/406,738 →
Method of Making an Integrated Circuit Incorporating Low Voltage and Hugh Voltage Semiconductor Devices
Patent: 4,475,280 →
Application: 06/450,687 →
Normally-Off Semiconductor Device with Low on Resistance and Circuit Analogue
Patent: 4,506,282 →
Application: 06/455,174 →
Power Chip Package
Patent: 4,538,170 →
Application: 06/455,186 →
Five-Transistor Static Memory Cell Implemental in Cmos/Bulk
Patent: 4,499,558 →
Application: 06/464,099 →
Processes and Gas Mixtures for the Reactive Ion Etching of Aluminum and Aluminum Alloys
Patent: 4,444,618 →
Application: 06/471,617 →
Normally-Off, Gate-Controlled Electrical Circuit with Low On-Resistance
Patent: 4,523,111 →
Application: 06/473,089 →
Cmos D-Type Latch Employing Six Transistors and Four Diodes
Patent: 4,521,695 →
Application: 06/478,014 →
Cmos Latch Cell Including Five Transistors, and Static Flip-Flops Employing the Cell
Patent: 4,484,087 →
Application: 06/478,015 →
Insulated-Gate Semiconductor Device with Low On-Resistance
Patent: 4,743,952 →
Application: 06/482,075 →
Method of Forming Refractory Metal Conductors of Low Resistivity
Patent: 4,471,004 →
Application: 06/489,613 →
Amplifying Gate Thyristor Having High Gate Sensitivity and High Dv/Dt Rating
Patent: 4,739,387 →
Application: 06/497,339 →
Semiconductor Device with Built-Up Low Resistance Contact
Patent: 4,505,029 →
Application: 06/501,745 →
Method for Manufacturing Insulated-Gate Semiconductor Devices with Integral Shorts
Patent: 4,466,176 →
Application: 06/502,834 →
Pinch Rectifier
Patent: 4,641,174 →
Application: 06/510,520 →
High Voltage Integrated Circuits
Application: 06/514,752 →
Fiber Optics Transducers for Sensing Parameter Magnitude
Patent: 4,472,628 →
Application: 06/530,328 →
Method of Reducing Electrostatic Charge on Ion-Implanted Wafer Devices
Patent: 4,786,814 →
Application: 06/532,898 →
Interconnection Structure for Polycrstalline Silicon Resistor and Methods of Making Same
Patent: 4,528,582 →
Application: 06/534,520 →
Field Effect Semiconductor Devices and Method of Making Same
Patent: 4,536,782 →
Application: 06/534,898 →
Method for Producing Eutectics as Thin Films Using a Quartz Lamp as a Heat Source in a Line Heater
Patent: 4,498,923 →
Application: 06/557,996 →
Method for Producing Eutectics as Thin Films Using a Line Heater
Patent: 4,498,924 →
Application: 06/557,997 →
Method for Producing Eutectics as Thin Films Using an Arc Lamp as a Heat Source in a Line Heater
Patent: 4,498,925 →
Application: 06/557,998 →
Method for Producing Eutectics as Thin Films Using a Laser Device as a Heat Source
Patent: 4,498,926 →
Application: 06/557,999 →
Diffraction Grating Wire Arrays in Parallel
Patent: 4,496,634 →
Application: 06/558,123 →
A Diffraction Grating Wire Arrays in Series
Patent: 4,492,738 →
Application: 06/558,124 →
Eutectic Fine Wire Arrays
Patent: 4,492,739 →
Application: 06/558,125 →
High Density Programmable Memory Array
Patent: 4,727,515 →
Application: 06/561,220 →
Method of Making an Insulated-Gate Semiconductor Device with Improved Shorting Region
Patent: 4,644,637 →
Application: 06/567,116 →
Solid State Zone Recrystallization of Semiconductor Material on an Insulator
Patent: 4,590,130 →
Application: 06/593,064 →
Circuit for Self-Commutated Turn-Off of Latched Devices, Such as of the Insulated-Gate Transistor/Rectifier Type
Patent: 4,620,258 →
Application: 06/595,179 →
Ohmic Contacts and Interconnects to Silicon and Method of Making Same
Patent: 4,871,617 →
Application: 06/595,800 →
Grain-Driven Zone-Melting of Silicon Films on Insulating Substrates
Patent: 4,585,493 →
Application: 06/615,403 →
Tape Automated Manufacture of Power Semiconductor Devices
Patent: 4,635,092 →
Application: 06/616,756 →
Method of Making Vertical Channel Field Controlled Device Employing a Recessed Gate Structure
Patent: 4,571,815 →
Application: 06/650,315 →
Forming Electrical Conductors in Long Microdiameter Holes
Patent: 4,628,174 →
Application: 06/651,014 →
Method for Nucleating and Growing Tungsten Films
Patent: 4,584,207 →
Application: 06/653,274 →
Fabrication of Integrated Circuit with Complementary, Dielectrically- Isolated, High Voltage Semiconductor Devices
Patent: 4,593,458 →
Application: 06/667,933 →
Power Semiconductor Devices with Increased Turn-Off Current Ratings and Limited Current Density in Peripheral Portions
Patent: 4,646,117 →
Application: 06/678,530 →
Normally-Off Semiconductor Device with Low on Resistance and Circuit Analogue
Patent: 4,645,957 →
Application: 06/685,632 →
Multiplexed-Access Scan Testable Integrated Circuit
Patent: 4,602,210 →
Application: 06/687,357 →
Method for Making Vertical Channel Field Controlled Device Employing a Recessed Gate Structure
Patent: 4,587,712 →
Application: 06/692,073 →
Methods of Making Self-Aligned Power Mosfet with Integral Source-Base Short
Patent: 4,598,461 →
Application: 06/693,643 →
Input Signal Conditioning Circuit
Patent: 4,730,131 →
Application: 06/695,297 →
Method of Making High Breakdown Voltage Semiconductor Device
Patent: 4,648,174 →
Application: 06/698,495 →
Bidirectional, High-Speed Power Mosfet Devices with Deep Level Recombination Centers in Base Region
Patent: 4,656,493 →
Application: 06/698,498 →
Method of Making an Integrated Circuit
Patent: 4,583,281 →
Application: 06/711,333 →
Nonplanar Ion- Sensitive Field - Effect Transistor Devices
Patent: 4,609,932 →
Application: 06/712,940 →
Flow Through Isfet and Method of Forming
Patent: 4,597,002 →
Application: 06/713,215 →
Method for Making Silicon Wafers
Patent: 4,597,822 →
Application: 06/717,364 →
Graded Extended Drain Concept for Reduced Hot Electron Effect
Patent: 4,680,603 →
Application: 06/722,640 →
Hybrid Extended Drain Concept for Reduced Hot Electron Effect
Patent: 4,613,882 →
Application: 06/722,642 →
Asymmetrical Field Controlled Thyristor
Patent: 4,937,644 →
Application: 06/756,478 →
Memory Cell with Diodes Providing Radiation Hardness
Patent: 4,725,875 →
Application: 06/782,581 →
High Voltage Semiconductor Devices Electrically Isolated from an Integrated Circuit Substrate
Patent: 4,661,838 →
Application: 06/790,716 →
Refractory Metal Capacitor Structures, Particularly for Analog Integrated Circuit Devices
Patent: 4,638,400 →
Application: 06/790,911 →
Video Coupler Device
Patent: 4,750,216 →
Application: 06/793,426 →
Lateral Insulated Gate Bipolar Transistors with Improbed Latch-Up Immunity
Patent: 4,963,951 →
Application: 06/803,049 →
Integrated Circuit for Controlling Power Converter by Frequency Modulation and Pulse Width Modulation
Patent: 4,685,040 →
Application: 06/805,651 →
Current Limited Insulated Gate Device
Patent: 4,641,162 →
Application: 06/807,597 →
Semiconductor Wafer with an Electrically-Isolated Semiconductor Device
Patent: 4,862,242 →
Application: 06/807,612 →
Multi-Driver Integrated Circuit
Patent: 4,779,161 →
Application: 06/820,808 →
Multilayer Interconnect and Method of Forming Same
Patent: 4,926,236 →
Application: 06/828,687 →
Bipolar Transistor with Transient Suppressor
Patent: 4,786,961 →
Application: 06/834,385 →
Method for Gate Electrode Fabrication and Symmetrical and Non-Symmetrical Self-Aligned Inlay Transistors Made Therefrom
Patent: 4,737,828 →
Application: 06/840,635 →
Method for Producing High-Aspect Ratio Hollow Diffused Regions in a Semiconductor Body and Diode Produced Thereby
Patent: 4,720,308 →
Application: 06/843,346 →
Unframed via Interconnection with Dielectric Etch Stop
Patent: 4,767,724 →
Application: 06/845,110 →
Semiconductor Chip Packages Having Solder Layers of Enhanced Durability
Patent: 4,769,744 →
Application: 06/851,275 →
Method of Making a Floating Gate Memory Cell
Patent: 4,735,919 →
Application: 06/852,289 →
Self-Aligned Inlay Transistor with or Without Source and Drain Self-Aligned Metallization Extensions
Patent: 4,677,736 →
Application: 06/853,108 →
Method of Fabricating Gold Bumps on Ic's and Power Chips
Patent: 4,750,666 →
Application: 06/853,255 →
Method of Forming a Semiconductor Structure
Patent: 4,722,912 →
Application: 06/856,277 →
Silicon-On-Sapphire Integrated Circuits
Patent: 4,735,917 →
Application: 06/856,280 →
Hybrid Extended Drain Concept for Reduced Hot Electron Effect
Patent: 4,691,433 →
Application: 06/857,283 →
Transistor Base Current Regulator
Patent: 4,684,878 →
Application: 06/860,814 →
Method of Making a Silicon-on-Insulator Transistor
Patent: 4,755,481 →
Application: 06/863,432 →
A Method of Fabricating a Substrate for a Semiconductor Chip Package
Patent: 4,737,217 →
Application: 06/866,530 →
Active Area Planarization with Self-Aligned Contacts
Patent: 4,849,377 →
Application: 06/866,648 →
Parallel Processing System Apparatus
Patent: 4,775,952 →
Application: 06/868,923 →
Hermetic Power Chip Packages
Patent: 4,646,129 →
Application: 06/872,792 →
Article Transfer System
Patent: 4,722,654 →
Application: 06/880,031 →
Passivation with a Low Oxygen Interface
Patent: 4,778,776 →
Application: 06/882,857 →
Electroless Nickel Plating Composition and Method
Patent: 4,695,489 →
Application: 06/890,050 →
Method and Apparatus for Improved Metal-Insulator-Semiconductor Device Operation
Patent: 4,729,005 →
Application: 06/891,058 →
Method for Determining Structural Defects in Semiconductor Wafers by Ultrasonic Microscopy
Patent: 4,741,212 →
Application: 06/891,170 →
Illuminator for Visual Inspection of Curved Specular Surfaces
Patent: 4,729,079 →
Application: 06/892,652 →
Power Semiconductor Device with Main Current Section and Emulation Current Section
Patent: 4,783,690 →
Application: 06/892,739 →
Arc Gap for Integrated Circuits
Patent: 4,794,437 →
Application: 06/895,365 →
Tape Automated Manufacture of Power Semiconductor Devices
Patent: 4,716,124 →
Application: 06/898,082 →
Memory Cell Circuit Having Radiation Hardness
Patent: 4,833,644 →
Application: 06/900,520 →
Radiation Hard Memory Cell Circuit with High Inverter Impedance Ratio
Patent: 4,760,557 →
Application: 06/904,156 →
Radiation Hard Memory Cell Structure with Drain Shielding
Patent: 4,989,061 →
Application: 06/904,271 →
Process of Forming a Resist Structure on Substrate Having Topo- Graphical Features Using Positive Photoresist Layer and Poly (Vinlypyrrolidone) Overlayer
Patent: 4,784,936 →
Application: 06/905,077 →
Method of Making Silicon-on-Sapphire Semiconductor Devices
Patent: 4,775,641 →
Application: 06/911,423 →
Igt and Mosfet Devices Having Reduced Channel Width
Patent: 4,803,533 →
Application: 06/913,785 →
Alignment Key and Method of Making the Same
Patent: 4,737,033 →
Application: 06/916,846 →
Method of Fabricating a Twin Tub Cmos Device
Patent: 4,707,455 →
Application: 06/935,372 →
Minimal Mask Process for Fabricating a Lateral Insulated Gate Semiconductor Device
Patent: 4,717,679 →
Application: 06/935,470 →
Memory Cell for a Dense Eprom
Patent: 4,947,221 →
Application: 06/940,167 →
Fabrication of Large Power Semiconductor Composite by Wafer Interconnection of Individual Devices
Patent: 4,816,422 →
Application: 06/947,151 →
Lateral Charge Control Semiconductor Device and Method of Fabrication
Patent: 4,796,070 →
Application: 07/003,678 →
Mosfet Structure with Substrate Coupled Source
Patent: 4,794,432 →
Application: 07/007,034 →
Method of Forming a Patterned Glass Layer Over the Surface of a Substrate
Patent: 4,732,838 →
Application: 07/013,529 →
Vertical Mosfet with Reduced Bipolar Effects
Patent: 4,837,606 →
Application: 07/014,196 →
Capacitor and Method for Making Same with High Yield
Patent: 4,731,695 →
Application: 07/015,478 →
Semiconductor Device with Source and Drain Depth Extenders and a Method of Making the Same
Patent: 4,786,955 →
Application: 07/018,314 →
Insulated Gate Semiconductor Device with Extra Short Grid and Method of Fabrication
Patent: 4,821,095 →
Application: 07/025,036 →
Isolation for Transistor Devices Having a Pilot Structure
Patent: 4,860,080 →
Application: 07/032,367 →
Vertical Double Diffused Metal Oxide Semiconductor Vdmos Device with Increased Safe Operating Area and Method
Patent: 4,801,986 →
Application: 07/033,940 →
Vertical Double Diffused Metal Oxide Semiconductor (Vdmos) Device Including High Voltage Junction Exhibiting Increased Safe Operating Area
Patent: 4,823,176 →
Application: 07/033,952 →
Semiconductor Device Having Turn-on and Turn-Off Capabilities
Patent: 4,816,892 →
Application: 07/036,058 →
Semiconductor Device Having Rapid Removal of Majority Carriers from an Active Base Region Thereof at Device Turn-Off and Method of Fabricating This Device
Patent: 4,782,379 →
Application: 07/040,693 →
Optical Reflectance Method of Examining a Simox Article
Patent: 4,766,317 →
Application: 07/041,565 →
Integrated Circuit for Controlling Power Converter by Frequency Modulation and Pulse Width Modulation
Patent: 4,733,104 →
Application: 07/045,494 →
Activation of Refractory Metal Surfaces for Electroless Plating
Patent: 4,746,375 →
Application: 07/047,739 →
Semiconductor Device That Minimizes the Leakage Currents Associated with the Parasitic Edge Transistors and a Method of Making the Same
Patent: 4,791,464 →
Application: 07/048,704 →
Treatment of Planarizing Layer in Multilayer Electron Beam Resist
Patent: 4,810,617 →
Application: 07/048,857 →
Adjustable Windage Method and Mask for Correction of Proximity Effect in Submicron Photolithography
Application: 07/049,744 →
Monolithically Integrated Semiconductor Device and Process for Fabrication
Patent: 4,801,985 →
Application: 07/051,359 →
Monolithically Integrated Insulated Gate Semiconductor Device
Patent: 4,847,671 →
Application: 07/051,424 →
Monolithically Integrated Lateral Insulated Gate Semiconductor Device
Patent: 4,888,627 →
Application: 07/051,427 →
Monolithically Integrated Semiconductor Device Having Bidirectional Conducting Capability and Method of Fabrication
Patent: 4,857,983 →
Application: 07/051,430 →
Method of Making Integrated Circuit with Pair of Mos Field Effect Transistors Sharing Common Source/Drain Region
Patent: 4,772,568 →
Application: 07/055,220 →
Zener Referenced Voltage Circuit
Patent: 4,774,452 →
Application: 07/055,545 →
Self-Aligned Barrier Metal and Oxidation Mask Method
Patent: 4,745,089 →
Application: 07/060,490 →
Method for Fabricating a Self-Aligned Lightly Doped Drain Semiconductor Device with Silicide
Application: 07/060,491 →
Method of Making a Power Ic Structure with Enhancement and/or Cmos Logic
Patent: 4,795,716 →
Application: 07/064,133 →
Metal Oxide Semiconductor Gated Turn Off Thyristor
Patent: 4,799,095 →
Application: 07/069,806 →
Method of Laser Soldering
Patent: 4,733,039 →
Application: 07/073,371 →
Buried Lateral Diode and Method for Making Same
Patent: 4,872,039 →
Application: 07/073,897 →
Semiconductor Device and Method of Fabrication
Patent: 4,810,665 →
Application: 07/077,711 →
Static Cmos Programmable Logic Array
Patent: 4,782,249 →
Application: 07/081,076 →
Photolithography Over Reflective Substrates Comprising a Titanium Nitride Layer
Patent: 4,810,619 →
Application: 07/084,464 →
Timing and Control Circuitry for Flash Analog to Digital Converters with Dynamic Encoders
Patent: 4,768,016 →
Application: 07/085,922 →
Lateral Metal-Oxide-Semiconductor Controlled Triacs
Patent: 4,857,977 →
Application: 07/088,353 →
Low Reflectance Conductor in an Integrated Circuit
Patent: 4,990,995 →
Application: 07/093,655 →
Insulated-Gate Semiconductor Device with Improved Base-to-Source Electrode Short and Method of Fabricating Said Short
Patent: 4,809,047 →
Application: 07/098,756 →
Method of Filling Interlevel Dielectric via or Contact Holes in Multilevel Vlsi Metallization Structures
Patent: 4,824,802 →
Application: 07/104,002 →
Impedance Transforming Circuit for Multibit Parallel Digital Circuits
Patent: 4,783,643 →
Application: 07/104,405 →
Determination of Substrate Temperature Used During Oxygen Implantation of Simox Wafer
Patent: 4,805,187 →
Application: 07/108,656 →
Method of Making Mo/Tiw or W/Tiw Ohmic Contacts to Silicon Same
Patent: 4,845,050 →
Application: 07/121,183 →
Method of Fabricating an Integrated Circuit Containing Bipolar and Mos Transistors
Patent: 4,764,482 →
Application: 07/124,129 →
Chip Carrier and Method of Fabrication
Patent: 4,809,135 →
Application: 07/124,393 →
Dense Eprom Having Serially Coupled Floating Gate Transistors
Patent: 4,933,904 →
Application: 07/134,585 →
High Temperature Annealing to Improve Simox Characteristics
Patent: 4,824,698 →
Application: 07/137,314 →
Metallization Contact System for Large Scale Integrated Circuits
Patent: 4,933,742 →
Application: 07/151,045 →
High Voltage Integrated Circuit Devices Electrically Isolated from an Integrated Circuit Substrate
Patent: 4,868,921 →
Application: 07/152,703 →
Soft Start Solid State Switch
Patent: 5,015,921 →
Application: 07/163,534 →
Gate Enhanced Rectifier
Application: 07/165,439 →
Structure for a Complementary-Symmetry Comfet Pair
Patent: 4,998,156 →
Application: 07/173,498 →
Fabrication Method and Structure for Field Isolation in Field Effect Transistors on Integrated Circuit Chips
Patent: 4,942,449 →
Application: 07/173,918 →
Self-Characterizing Analog-to-Digital Converter
Patent: 4,897,650 →
Application: 07/178,045 →
Simple Automated Discretionary Bonding of Multiple Parallel Elements
Patent: 4,814,283 →
Application: 07/179,441 →
Cell Stack for Variable Digit Width Serial Architecture
Patent: 4,951,221 →
Application: 07/182,602 →
Low Noise, High Frequency Synchronous Rectifier
Patent: 4,903,189 →
Application: 07/186,983 →
Metal Oxide Semiconductor Gated Turn-Off Thyristor Including a Low Lifetime Region
Patent: 4,982,258 →
Application: 07/188,888 →
Method of Making Symmertical Blocking High Voltage Breakdown Semiconductor Device
Patent: 4,904,609 →
Application: 07/190,903 →
Graded Extended Drain Concept for Reduced Hot Electron Effect
Patent: 4,859,620 →
Application: 07/196,416 →
Bipolar Transistor with Field Shields
Patent: 4,864,379 →
Application: 07/197,098 →
Memory Cell Structure Having Radiation Hardness
Patent: 4,903,094 →
Application: 07/218,425 →
Method of Fabricating Self Aligned Semiconductor Devices
Patent: 4,883,767 →
Application: 07/220,353 →
Power Bipolar Transistor Device with Integral Antisaturation Diode
Patent: 4,969,027 →
Application: 07/220,649 →
Power Transistor Structure with High Speed Integral Antiparallel Schottky Diode
Patent: 4,967,243 →
Application: 07/221,482 →
Protective Clamp for Mos Gated Devices
Patent: 4,890,143 →
Application: 07/225,320 →
Hermetically Sealed Housing
Patent: 4,901,135 →
Application: 07/232,197 →
Complementary Circuit and Structure with Common Substrate
Patent: 4,910,563 →
Application: 07/232,243 →
Self Packaging Chip Mount
Patent: 4,908,736 →
Application: 07/235,087 →
Semiconductor Devices Exhibiting Minimum On-Resistance
Patent: 4,941,026 →
Application: 07/239,014 →
Mct Providing Turn-Off Control of Arbitrarily Large Currents
Patent: 4,958,211 →
Application: 07/239,678 →
Method of Making Direct Bonded Wafers Having a Void Free Interface
Patent: 4,939,101 →
Application: 07/240,332 →
Method for Fabricating a Self-Aligned Lightly Doped Drain Semiconductor Device with Silicide
Patent: 4,933,994 →
Application: 07/243,200 →
High Voltage Semiconductor Devices with Reduced On-Resistance
Patent: 4,942,440 →
Application: 07/243,210 →
Insulated Gate Transistor with Vertical Integral Diode and Method of Fabrication
Patent: 4,933,740 →
Application: 07/243,211 →
Radiation Hard Memory Cell Having Monocrystalline and Non-Monocrysta- Lline Inverters
Patent: 4,872,141 →
Application: 07/243,367 →
A Buried Oxide Field Isolation Structure with Composite Dielectric
Patent: 4,903,107 →
Application: 07/246,068 →
Apparatus and Method for Optical Dimension Measurement Using Interference of Scattered Electromagnetic
Patent: 4,964,726 →
Application: 07/250,249 →
Circuit Including a Combined Insulated Gate Bipolar Transistor/Mosfet
Patent: 4,901,127 →
Application: 07/254,897 →
Adjustable Windage Method and Mask for Correction of Proximity Effect in Submicron Photolithography
Patent: 4,895,780 →
Application: 07/265,285 →
Method of Fabricating a Field Effect Semiconductor Device Having a Self-Aligned Structure
Patent: 5,082,795 →
Application: 07/267,757 →
Insulated Gate Bipolar Transistor with Improved Latch-Up Current Level and Safe Operating Area
Patent: 4,994,871 →
Application: 07/279,392 →
Mos Protection Device
Patent: 4,980,741 →
Application: 07/308,498 →
Method of Self- Packing an Ic Chip
Patent: 4,914,812 →
Application: 07/312,849 →
Mos-Pilot Structure for an Insulated Gate Transistor
Patent: 4,980,740 →
Application: 07/329,034 →
Power Field Effect Devices Having Small Cell Size and Low Contact Resistance
Patent: 4,998,151 →
Application: 07/337,684 →
Method of Making High Breakdown Voltage Semiconductor Device
Patent: 4,927,772 →
Application: 07/358,057 →
Power Field Effect Devices Having Low Gate Sheet Resistance and Low Ohmic Contact Resistance and Method of Fabrication
Patent: 4,985,740 →
Application: 07/359,811 →
Hermetic Package Having a Lead Extending Through an Aperture in the Package Lid and Packaged Semiconductor Chip
Patent: 5,103,290 →
Application: 07/367,525 →
High Current Hermetic Package Having a Lead Extending Through the Package Lid and a Packaged Semiconductor Chip
Patent: 5,028,987 →
Application: 07/375,569 →
Hermetic Package and Packaged Semiconductor Chip Having Closely Spaced Leads Extending Through the Package Lid
Patent: 5,166,773 →
Application: 07/375,636 →
High Current Hermetic Package Including an Internal Foil and Having a Lead Extending Through the Package Lid and a Packaged Semiconductor Chip
Patent: 5,018,002 →
Application: 07/375,641 →
Symmetrical Blocking High Voltage Semiconductor Device and Method of Fabrication
Patent: 5,041,896 →
Application: 07/376,073 →
Complementary Circuit and Structure with Common Substrate
Patent: 4,937,467 →
Application: 07/411,424 →
Field Controlled Diode (Fcd) Having Mos Trench Gates
Patent: 4,994,883 →
Application: 07/416,171 →
Symmetrical Blocking High Voltage Breakdown Semiconductor Device and Method of Fabrication
Patent: 4,999,684 →
Application: 07/435,632 →
High Voltage Integrated Circuits
Patent: 4,958,210 →
Application: 07/440,457 →
Method of Making a Buried Oxide Field Isolation Structure
Patent: 4,983,537 →
Application: 07/440,962 →
Mo/Ti Contact to Silicon
Patent: 4,981,816 →
Application: 07/445,130 →
Integrated Circuit with Stacked Mos Field Effect Transistors
Patent: 4,999,691 →
Application: 07/453,090 →
Enhanced Direct Bond Copper Process and Structure
Patent: 4,996,116 →
Application: 07/454,547 →
Gate Enhanced Rectifier
Patent: 4,969,028 →
Application: 07/492,377 →
Direct Thermocompression Bonding for Thin Electronic Power Chips
Patent: 5,184,206 →
Application: 07/603,495 →
Batch Assembly of High Density Hermetic Packages for Power Semiconductor Chips
Patent: 5,139,972 →
Application: 07/661,946 →
A Method of Packaging a Semiconductor Chip in a Low Inductance Package
Patent: 5,105,536 →
Application: 07/690,409 →
Method of Forming Hermetic Package Having a Lead Extending Through an Aperture in the Package Lid Packaged Semiconductor Chip
Patent: 5,135,890 →
Application: 07/765,286 →
Direct Bonded Symmetric-Metallic-Laminate/Substrate Structures
Patent: 5,100,740 →
Application: 07/777,495 →
Hermetic Package and Packaged Semiconductor Chip Having Closely Spaced Leads Extending Through the Package Lid
Patent: 5,209,390 →
Application: 07/935,805 →
Method for Forming Semiconductor Electrical Contacts Using Metal Foil and Thermocompression Bonding
Patent: 5,206,186 →
Application: 07/950,553 →
Integrated Heat Sink Having a Sinuous Fluid Channel for the Thermal Dissipation of Semiconductor Modules
Patent: 5,293,070 →
Application: 07/973,603 →
Direct Thermocompression Bonding for Thin Electronic Power Chips
Patent: 5,304,847 →
Application: 08/007,300 →
Fet, Igbt and Mct Structures to Enhance Operating Characteristics
Patent: 6,656,774 →
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Related Assignments (21)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. Sep 15, 1980
From: REIHL ROBERT F.; WANG KANG-LUNG
To: GENERAL ELECTRIC COMPANY
Reel/Frame 003816/0213 →
Assignment of Assignors Interest. Sep 15, 1980
From: CHOW TAT-SING P.; GHEZZO MARIO
To: GENERAL ELECTRIC COMPANY
Reel/Frame 003816/0248 →
Assignment of Assignors Interest. Sep 15, 1980
From: GHEZZO MARIO
To: GENERAL ELECTRIC COMPANY
Reel/Frame 003816/0011 →
Assignment of Assignors Interest. Oct 1, 1980
From: GHEZZO MARIO; JERDONEK RONALD T.
To: GENERAL ELECTRIC COMPANY
Reel/Frame 003820/0051 →
Assignment of Assignors Interest. Oct 27, 1980
From: RANSLEY RICHARD G.; SAHM WILLIAM H. III
To: GENERAL ELECTRIC COMPANY, A NY CORP.
Reel/Frame 003838/0408 →
Assignment of Assignors Interest. Nov 21, 1980
From: FICHOT JULIE Y.; ROESCH ALFRED
To: GENERAL ELECTRIC COMPANY, A NY CORP.
Reel/Frame 003831/0408 →
Assignment of Assignors Interest. Dec 24, 1980
From: RAGONESE LOUIS J.; SCHMITZ NICHOLAS A.; BEVACQUA SAVERIO F.; OWYANG KING
To: GENERAL ELECTRIC COMPANY
Reel/Frame 003844/0802 →
Assignment of Assignors Interest. Feb 7, 1981
From: CARLSON RICHARD O.; YERMAN ALEXANDER J.
To: GENERAL ELECTRIC COMPANY, A CORP. OF NY.
Reel/Frame 003871/0312 →
Assignment of Assignors Interest. Mar 18, 1981
From: ANTHONY THOMAS R.
To: GENERAL ELECTRIC COMPANY, A CORP. OF
Reel/Frame 003875/0966 →
Assignment of Assignors Interest. Mar 20, 1981
From: CLINE HARVEY E.
To: GENERAL ELECTRIC COMPANY, A CORP. OF NY.
Reel/Frame 003873/0494 →
Assignment of Assignors Interest. Apr 3, 1981
From: WEBSTER HAROLD F.
To: GENERAL ELECTRIC COMPANY, A CORP. OF
Reel/Frame 003876/0093 →
Assignment of Assignors Interest. Apr 13, 1981
From: CLINE HARVEY E.
To: GENERAL ELECTRIC COMPANY, A CORP. OF NY
Reel/Frame 003881/0435 →
Assignment of Assignors Interest. Apr 16, 1981
From: JOCHYM ERIC P.
To: GENERAL ELECTRIC COMPANY, A CORP. OF N.Y.
Reel/Frame 003879/0654 →
Assignment of Assignors Interest. Apr 24, 1981
From: BALIGA BANTVAL J.; ADLER MICHAEL S.
To: GENERAL ELECTRIC COMPANY, A CORP. OF NY.
Reel/Frame 003880/0432 →
Assignment of Assignors Interest. May 7, 1981
From: OLIVER JAMES D. JR.
To: GENERAL ELECTRIC COMPANY, A CORP.OF N.Y.
Reel/Frame 003888/0095 →
Assignment of Assignors Interest. Jun 22, 1981
From: GRIFFING, BRUCE F.; JOHNSON, PETER D.; JOHNSON, ROGER N.
To: GENERAL ELECTRIC COMPANY
Reel/Frame 003896/0406 →
Assignment of Assignors Interest. Jul 21, 1981
From: ANTHONY, THOMAS R.
To: GENERAL ELECTRIC COMPANY
Reel/Frame 003901/0745 →
Security Interest Nov 8, 1999
From: INTERSIL CORPORATION
To: CREDIT SUISSE FIRST BOSTON, AS COLLATERAL AGENT
Reel/Frame 010351/0410 →
Document Previously Recorded as Reel/Frame 010255/0405 Recorded on September 11, 1999 Contained Error in Property Number (U.S. Patent No. 5,210,471). Property Should Not Have Appeared on Original Schedule. Please Remove and Correct on Stated Reel. Jun 15, 2000
From: HUBBELL INCORPORATED
To: HUBBELL INCORPORATED
Reel/Frame 010701/0873 →
Intellectual Property Partial Release Mar 16, 2001
From: CREIDT SUISSE FIRST BOSTON
To: INTERSIL HOLDING CORPORATION
Reel/Frame 011667/0166 →
Reassignment of Patent Applications Jul 16, 2001
From: INTERSIL CORPORATION
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 012002/0206 →