IP Library › Assignment 010351/0410
Patent Assignment
Reel/Frame 010351/0410

Security Interest

Recorded: 1999-11-08 Pages: 122
Assignor
INTERSIL CORPORATION
Executed: 1999-08-13
Assignee
CREDIT SUISSE FIRST BOSTON, AS COLLATERAL AGENT
11 MADISON AVENUE, NEW YORK, NEW YORK, 10010
Covered Properties (1479)
Ballasted Gate Controlled Semiconductor Device
Patent: 4,561,008 →
Application: 05/870,484 →
Five Transistor Cmos Memory Cell Including Diodes
Patent: 4,724,530 →
Application: 05/948,103 →
Radiation Hard, High Emitter-Base Breakdown Bipolar Transistor
Patent: 4,881,111 →
Application: 05/973,822 →
Thyristor Cathode and Transistor Emitter Structures with Insulator Islands
Patent: 4,581,626 →
Application: 06/028,576 →
Vertical Mosfet with Reduced Turn-on Resistance
Patent: 4,366,495 →
Application: 06/063,809 →
Silicon Mos Inductor
Patent: 4,282,537 →
Application: 06/068,013 →
Mnos Memory Device and Method of Manufacture
Patent: 4,305,086 →
Application: 06/070,020 →
Blocked Source Node Field-Effect Circuitry
Patent: 4,253,162 →
Application: 06/070,509 →
Differential-Input Amplifier Circuit
Patent: 4,272,728 →
Application: 06/070,510 →
Starting Circuit for Low Power Oscillator Circuit
Patent: 4,282,496 →
Application: 06/070,703 →
Free Hold Down of Wafers for Material Removal
Patent: 4,258,508 →
Application: 06/072,430 →
Measurement of a Gas Constituent by a Mass Spectrometer
Patent: 4,260,886 →
Application: 06/073,199 →
Method of Defining a Photoresist Layer
Patent: 4,239,790 →
Application: 06/075,162 →
Positive Resist for Electron Beam and X-Ray Lithography and Method of Using Same
Patent: 4,262,083 →
Application: 06/076,673 →
Operational Transconductance Amplifiers with Non-Linear Component Current Amplifiers
Patent: 4,267,519 →
Application: 06/076,674 →
Method of Fabricating Lateral Pnp Transistors Ulizing Selective Diffusion and Counter Doping
Patent: 4,283,236 →
Application: 06/077,234 →
Relative Humidity Measurement
Patent: 4,227,411 →
Application: 06/077,913 →
Fabrication of an Integrated Injection Logic Device with Narrow Base Width
Patent: 4,244,001 →
Application: 06/080,101 →
Look Ahead High Speed Circuitry
Patent: 4,242,738 →
Application: 06/081,040 →
Amplifier Circuit Having Controllable Gain
Patent: 4,305,044 →
Application: 06/081,087 →
Temperature Gradient Means in Reactor Tube of Vapor Deposition Apparatus
Patent: 4,256,052 →
Application: 06/081,193 →
Chuck for Use in Testing of Semiconductor Pellets
Patent: 4,327,325 →
Application: 06/081,194 →
Vertical Fuse and Method of Fabrication
Patent: 4,312,046 →
Application: 06/081,978 →
Complementary Igfet Buffer with Improved Bipolar Output
Patent: 4,301,383 →
Application: 06/082,185 →
Programmable Threshold Switchables Resistive Memory Cell Array
Patent: 4,236,231 →
Application: 06/082,505 →
Two Switchable Resistive Element Per Cell Memory Array
Patent: 4,272,833 →
Application: 06/082,506 →
Method of Making an Impatt Diode
Patent: 4,230,505 →
Application: 06/082,733 →
Method of Detecting a Thin Insulating Film Over a Conductor
Patent: 4,296,370 →
Application: 06/083,640 →
Overload Protection Circuit for Output Driver
Patent: 4,329,600 →
Application: 06/084,711 →
Two Input Sense Circuit
Patent: 4,321,492 →
Application: 06/084,712 →
Gate Injected Floating Gate Memory Device
Patent: 4,253,106 →
Application: 06/086,313 →
Multi-Mode Oscillator
Patent: 4,250,500 →
Application: 06/087,447 →
Means to Orbit and Rotate Target Wafers Supported on Planet Member
Patent: 4,284,033 →
Application: 06/089,858 →
Partially Devitrified Porcelain Composition and Articles Prepared with Same
Patent: 4,256,796 →
Application: 06/091,091 →
Low Leakage N-Channel Sos Transistors and Method of Making Them
Patent: 4,252,574 →
Application: 06/093,011 →
Method of Detecting a Cathodic Corrosion Site on a Metallized Substrate
Patent: 4,278,508 →
Application: 06/093,214 →
Method of Manufacturing Submicron Channel Transistors
Patent: 4,313,782 →
Application: 06/094,215 →
Amplifier with Cross-Over Current Control
Patent: 4,297,644 →
Application: 06/096,739 →
Positive Resist Medium and Method of Employing Same
Patent: 4,262,073 →
Application: 06/096,973 →
Class Ab Push-Pull Amplifiers
Patent: 4,335,360 →
Application: 06/097,040 →
Method for Manufacturing a Self-Aligned Contact in a Grooved Semiconductor Surface
Patent: 4,268,537 →
Application: 06/099,598 →
Push-Push Resonant Power Inverter
Patent: 4,250,541 →
Application: 06/101,165 →
Optically Testing the Lateral Dimensions of a Pattern
Patent: 4,303,341 →
Application: 06/101,166 →
Reference Current Supply Circuits
Patent: 4,282,478 →
Application: 06/101,848 →
Class Ab Push-Pull Quasi-Linear Amplifiers
Patent: 4,295,101 →
Application: 06/102,131 →
Circuit with Dual-Purpose Terminal
Patent: 4,350,906 →
Application: 06/102,574 →
Low Power Switch Closure Sensing Circuit
Patent: 4,303,907 →
Application: 06/103,924 →
Compensation for Transistor Output Resistance
Patent: 4,311,967 →
Application: 06/104,372 →
Method for Qualifying Biased Integrated Circuits on a Wafer Level
Patent: 4,288,911 →
Application: 06/106,127 →
Method of Making Schottky Barrier Diode by Ionimplantation and Impurity Diffusion
Patent: 4,260,431 →
Application: 06/106,128 →
Method for Qualifying Biased Burn-in Integrated Circuits on a Wafer Level
Patent: 4,281,449 →
Application: 06/106,339 →
Battery Test System, as for Smoke Detector Alarm
Patent: 4,251,811 →
Application: 06/106,656 →
Small Signal Memory System with Reference Signal
Patent: 4,270,190 →
Application: 06/106,882 →
Signal Comparison Circuit
Patent: 4,348,596 →
Application: 06/107,403 →
Circuit for Reducing the Loading Effect of an Insulated-Gate Field-Effect Transistor (Igfet) on a Signal Source
Patent: 4,281,400 →
Application: 06/108,222 →
Solid State Relay
Patent: 4,268,843 →
Application: 06/112,397 →
Low Thermal Coefficient Semiconductor Device
Patent: 4,319,257 →
Application: 06/112,618 →
System for Short Circuit Protection Using Electronic Logic in a Feed Back Arrangement
Patent: 4,305,106 →
Application: 06/113,430 →
Method for Forming Buried Contact Complementary Mos Devices
Patent: 4,276,688 →
Application: 06/113,505 →
Composite Conductive Structures in Integrated Circuits and Method of Making Same
Patent: 4,263,058 →
Application: 06/115,069 →
Extended Drain Self-Aligned Silicon Gate Mosfet
Patent: 4,318,216 →
Application: 06/116,789 →
Method of Manufacturing Short Channel Mos Devices
Patent: 4,263,057 →
Application: 06/116,896 →
Radiation Heated Reactor for Chemical Vapor Deposition on Substrates
Patent: 4,263,872 →
Application: 06/117,236 →
Use of Silicide to Bridge Unwanted Polycrystalline Silicon P-N Junction
Patent: 4,333,099 →
Application: 06/118,089 →
Series Voltage Regulators for Developing Temperature-Compensated Voltages
Patent: 4,282,477 →
Application: 06/120,471 →
Fast Level Shift Circuits
Patent: 4,314,166 →
Application: 06/123,714 →
Fabrication of Complementary Bipolar Transistors and Cmos Devices with Poly Gates
Patent: 4,299,024 →
Application: 06/124,201 →
Position Sensing and Display Means
Patent: 4,294,321 →
Application: 06/125,118 →
Latching Transistor
Patent: 4,356,503 →
Application: 06/125,413 →
Method of Applying Thin Metal Deposits to a Substrate
Patent: 4,297,393 →
Application: 06/125,639 →
Differential-Input Amplifier Circuitry with Increased Common-Mode Voltage Range
Patent: 4,345,213 →
Application: 06/125,645 →
Current Dividers Using Emitter-Coupled Transistor Pairs
Patent: 4,284,945 →
Application: 06/128,872 →
Method of Fabricating Mesa Bipolar Memory Cell Utilizing Epitaxial Deposition, Substrate Removal and Special Metallization
Patent: 4,292,730 →
Application: 06/129,913 →
Method of Improving Silicon Crystal Perfection in Silicon on Sapphire Devices
Patent: 4,279,688 →
Application: 06/131,046 →
Amplifier Using Lateral and Vertical Transistors
Patent: 4,334,196 →
Application: 06/131,518 →
Cmos Device with Silicided Sources and Drains and Method
Patent: 4,336,550 →
Application: 06/132,138 →
Four Terminal Voltage Tripler for Monolithic Lcd Clock Circuit
Patent: 4,290,100 →
Application: 06/132,819 →
Centering Support for a Rotatable Wafer Support Susceptor
Patent: 4,275,282 →
Application: 06/132,878 →
Method for Measuring the Drift Mobility in Doped Semiconductors
Patent: 4,319,187 →
Application: 06/133,253 →
Differential-Input Complementary Field-Effect Transistor Amplifier
Patent: 4,333,057 →
Application: 06/133,254 →
A Method for the Manufacture of Boards Having Interconnections Between the Top and Bottom Surfaces
Patent: 4,328,614 →
Application: 06/133,255 →
Power Mosfet with an Anode Region
Patent: 4,364,073 →
Application: 06/133,902 →
High Speed Integrating Analog-to-Digital Converter
Patent: 4,395,701 →
Application: 06/134,153 →
Method of Manufacturing Submicron Channel Transistors
Patent: 4,312,680 →
Application: 06/136,157 →
Method and Apparatus for Thermo-Compression Diffusion Bonding
Patent: 4,252,263 →
Application: 06/139,177 →
Three-Condition Display System
Patent: 4,321,543 →
Application: 06/139,714 →
Method of Solder Reflow Assembly
Patent: 4,334,646 →
Application: 06/141,100 →
Method of Fabricating Surface Contacts for Buried Layer into Dielectric Isolated Islands
Patent: 4,290,831 →
Application: 06/141,504 →
Successive Approximation Analog-to-Digital Converter Using Non-Binary Series
Patent: 4,336,526 →
Application: 06/142,644 →
Precharge Circuit
Patent: 4,352,031 →
Application: 06/143,025 →
Circuitry for Generating Electric Signals with Proportional, Opposite- Sense Rates of Change
Patent: 4,322,691 →
Application: 06/143,346 →
Biasing of Transistor Amplifier Cascades
Patent: 4,334,198 →
Application: 06/143,504 →
Operational Amplifier Employing Complementary Field-Effect Transistors
Patent: 4,333,058 →
Application: 06/144,291 →
Random Access Memory with Volatile and Non-Volatile Storage
Patent: 4,354,255 →
Application: 06/144,922 →
Memory Circuit with Means for Compensating for Inversion of Stored Data
Patent: 4,337,522 →
Application: 06/145,324 →
Method of Treating Sipos Passivated High Voltage Semiconductor Device
Patent: 4,297,149 →
Application: 06/146,380 →
Method of Laying Out an Integrated Circuit with Specific Alignment of the Collector Contact with the Emitter Region
Patent: 4,272,882 →
Application: 06/147,574 →
Vertical Channel Field Effect Transistor
Patent: 4,343,015 →
Application: 06/149,936 →
Transistor Amplifiers Exhibiting Low Input Offset Potentials
Patent: 4,360,785 →
Application: 06/153,627 →
Reference Poential Generating Circuits
Patent: 4,302,718 →
Application: 06/153,628 →
Plural Output Switched Current Amplifier as for Driving Light Emitting Diodes
Patent: 4,417,240 →
Application: 06/153,629 →
Wafer and Boule Protection During the Blade Return Stroke of a Wafer Saw
Patent: 4,326,494 →
Application: 06/153,632 →
Method and Apparatus for Determining Minority Carrier Diffusion Length in Semiconductors
Patent: 4,333,051 →
Application: 06/153,920 →
Method for Determining Silicon Content in Layers of Aluminum and Silicon
Patent: 4,282,266 →
Application: 06/154,598 →
Low Leakage N-Channel Sos Transistors and Method of Making Them
Patent: 4,393,572 →
Application: 06/154,601 →
Wafer and Boule Protection During the Blade Return Stroke of a Wafer Saw
Patent: 4,287,256 →
Application: 06/155,999 →
Etching Tank in Which the Solution Circulates by Convection
Patent: 4,302,273 →
Application: 06/156,889 →
Method of Serialization of Dice
Patent: 4,409,686 →
Application: 06/159,750 →
High Breakdown Voltage Semiconductor Device
Patent: 4,374,389 →
Application: 06/159,813 →
Semiconductor Power Device Having Second Breakdown Protection
Patent: 4,291,324 →
Application: 06/161,453 →
Digital Timing System for Spark Advance
Patent: 4,375,209 →
Application: 06/161,454 →
Wettable Carrewe in Gas Drying System for Wafers
Patent: 4,318,749 →
Application: 06/162,086 →
Compensation of Base-Current-Related Error in Current Mirror Amplifier Circuitry
Patent: 4,345,216 →
Application: 06/162,939 →
Plasma Etching Device and Process
Patent: 4,304,983 →
Application: 06/163,148 →
Electron Flood Exposure Apparatus
Patent: 4,321,470 →
Application: 06/164,069 →
Current Mirror Amplifiers with Programmable Gain
Patent: 4,361,816 →
Application: 06/164,139 →
Self Aligned Aluminum Polycrystalline Silicon Contact
Patent: 4,380,773 →
Application: 06/164,345 →
Power Protection Circuit for Transistors
Patent: 4,355,341 →
Application: 06/164,347 →
Electrically Programmable Logic Array
Patent: 4,313,106 →
Application: 06/164,677 →
Method of Manufacturing Bulk Cmos Integrated Circuits
Patent: 4,295,266 →
Application: 06/164,681 →
Operational Amplifier with Programmable Gain
Patent: 4,361,815 →
Application: 06/164,682 →
Multi-Mode Circuit
Patent: 4,317,110 →
Application: 06/164,683 →
Rf Heating Coil Construction for Stack of Susceptors
Patent: 4,339,645 →
Application: 06/165,740 →
Semiconductor Power Device Incorporating a Schottky Barrier Diode Between Base and Emitter of a Pnp Device
Patent: 4,253,105 →
Application: 06/165,760 →
High-Current, High-Voltage Semiconductor Devices Having a Metallurgical Grade Substrate
Patent: 4,383,268 →
Application: 06/166,347 →
Current Regulating Circuitry
Patent: 4,300,091 →
Application: 06/167,696 →
Differential Linear to Digital Translator
Patent: 4,368,395 →
Application: 06/170,291 →
Method of Making Semiconductor Device with Passivated Rectifying Junctions Having Hydrogenated Amorphous Regions
Patent: 4,315,782 →
Application: 06/170,813 →
Method for End Ppint Detection in a Plasma Etching Process
Patent: 4,328,068 →
Application: 06/171,271 →
Dual Output Switching Circuit
Patent: 4,337,423 →
Application: 06/171,833 →
Method for Fabricating Adjacent Conducting and Insulating Regions in a Film by Laser Irradiation
Patent: 4,339,285 →
Application: 06/172,757 →
Apparatus and Method for Neutralizing the Beam in an Ion Implanter
Patent: 4,361,762 →
Application: 06/173,630 →
Pulse Counter Type Circuit for Power-Up Indication
Patent: 4,365,174 →
Application: 06/174,184 →
Method for Forming an Improved Gate Member Utilizing Special Masking and Oxidation to Eliminate Projecting Points on Silicon Islands
Patent: 4,277,884 →
Application: 06/174,845 →
Method of Forming an Improved Gate Member for a Gate Injected Floating Gate Memory Device
Patent: 4,334,347 →
Application: 06/175,757 →
Temperature-Correction Network for Extrapolated Band-Gap Voltage Reference Circuit
Patent: 4,325,017 →
Application: 06/177,913 →
Bow-Correction Network with Multiple Corrections for Extrapolated Band -Gap Voltage Reference Circuit
Patent: 4,325,018 →
Application: 06/177,915 →
Duty Cycle Generator with Improved Resolution
Patent: 4,365,202 →
Application: 06/180,903 →
Susceptor for Heating Semiconductor Substrates
Patent: 4,322,592 →
Application: 06/181,376 →
Digital Timing System for Spark Advance
Patent: 4,408,296 →
Application: 06/181,941 →
Megasonic Jet Cleaner Apparatus
Patent: 4,326,553 →
Application: 06/181,985 →
Thin Film Thickness Monitor
Patent: 4,355,903 →
Application: 06/181,990 →
Field Effect Transistor Amplifier with Variable Gain Control
Patent: 4,353,036 →
Application: 06/182,787 →
Switch Closure Sensing Circuit
Patent: 4,318,087 →
Application: 06/184,952 →
Method of Making Low Resistance Contacts in Semiconductor Devices by Ion Induced Silicides
Patent: 4,339,869 →
Application: 06/187,043 →
Method of Making Integrated Circuits
Patent: 4,333,964 →
Application: 06/187,430 →
Method of Making Integrated Circuits
Patent: 4,333,965 →
Application: 06/187,501 →
Noise Protection Circuits
Patent: 4,339,809 →
Application: 06/188,887 →
Method and Apparatus for Determining the Quality of a Semiconductor Surface
Patent: 4,352,016 →
Application: 06/189,348 →
Apparatus for Determining the Quality of a Semiconductor Surface
Patent: 4,352,017 →
Application: 06/189,356 →
Radiation Hardened-Self Aligned Cmos and Method of Fabrication
Patent: 4,402,002 →
Application: 06/190,515 →
Bridge Amplifiers Employing Complementary Field-Effect Transistors
Patent: 4,355,287 →
Application: 06/192,363 →
Gated Oscillator Including Initialization Apparatus for Enhancing Periodicity
Patent: 4,365,212 →
Application: 06/192,364 →
Integrated Circuit and Method of Making Same
Patent: 4,378,565 →
Application: 06/192,881 →
Borosilicate Glass Frit with Mgo and Bao
Patent: 4,355,115 →
Application: 06/193,712 →
Method of Reducing Edge Current Leakage in N Channel Silicon-on-Sapphire Devices
Patent: 4,313,809 →
Application: 06/197,286 →
Electrochromic Films Having Improved Etch Resistance
Patent: 4,475,795 →
Application: 06/198,683 →
Method of and Apparatus for Outgassing Raw Material Used to Grow Crystals
Patent: 4,305,725 →
Application: 06/198,833 →
Fabrication of Isolated Regions for Use in Self - Aligning Device Process Utilizing Selective Oxidation
Patent: 4,670,769 →
Application: 06/200,386 →
Use of Dispersed Solids as Fillers in Polymeric Materials to Provide Material for Semiconductor Junction Passivation
Patent: 4,331,970 →
Application: 06/201,143 →
Quantizing Circuits Using a Charge Coupled Device with a Feedback Channel
Patent: 4,369,378 →
Application: 06/201,191 →
Fiber Optic Coupler
Patent: 4,377,322 →
Application: 06/201,350 →
Radiation Heated Reactor Process for Chemical Vapor Deposition on Substrates
Patent: 4,401,689 →
Application: 06/201,437 →
Laminated Conducting Film on an Integrated Circuit Substrate and Method of Forming the Laminate
Patent: 4,302,498 →
Application: 06/201,438 →
Method of Forming a Mesa in a Semiconductor Device with Subsequent Separation into Individual Devices
Patent: 4,355,457 →
Application: 06/201,826 →
Current Amplifier
Patent: 4,380,740 →
Application: 06/202,485 →
Photocurrent Compensation for Electronic Circuitry Exposed to Ionizing Radiation
Patent: 4,380,741 →
Application: 06/205,341 →
Testing Semiconductor Furnaces for Heavy Metal Contamination
Patent: 4,420,722 →
Application: 06/206,715 →
Positive Resist for Electron Beam and X-Ray Lithography and Method of Using Same
Patent: 4,330,671 →
Application: 06/206,716 →
Power Transformer with High Coupling Coefficient
Patent: 4,320,373 →
Application: 06/207,720 →
Monitor for Oxygen Concentration in Aluminum-Based Films
Patent: 4,348,886 →
Application: 06/208,704 →
Thermal Stress Relieving Bimetallic Plate
Patent: 4,427,993 →
Application: 06/209,001 →
New Water-Based Photoresists Using Stilbene Compounds as Crosslinking Agents
Patent: 4,299,910 →
Application: 06/209,535 →
Self-Quenching Circuit
Patent: 4,382,192 →
Application: 06/211,342 →
Vehicle Multiplex System
Patent: 4,370,561 →
Application: 06/211,343 →
Circuit and Method for Duty Cycle Control
Patent: 4,355,283 →
Application: 06/211,349 →
Mask Alignment Scheme for Laterally and Totally Dielectrically Isolated Integrated Circuits
Patent: 4,309,813 →
Application: 06/212,799 →
Transistor with Improved Second Breakdown Capability
Patent: 4,388,634 →
Application: 06/212,813 →
Retainer Ring for Securing Substrates in a Vacuum Deposition System
Patent: 4,344,383 →
Application: 06/215,004 →
Xenon Flash Lamp Shield
Patent: 4,378,583 →
Application: 06/215,089 →
Aqueous Developable Poly (Olefin Sulfone) Terpolymers
Patent: 4,341,861 →
Application: 06/219,517 →
Integrated Circuit Incorporating Low Voltage and High Voltage Semiconductor Devices
Patent: 4,412,142 →
Application: 06/219,824 →
Semiconductor Device Passivated with Phosilicate Glass Over Silicon Nitride
Patent: 4,668,973 →
Application: 06/221,367 →
Amorphous Devices and Interconnect System and Method of Fabrication
Patent: 4,471,376 →
Application: 06/224,931 →
Temperature-Independent Current Trimming Arrangement
Patent: 4,366,444 →
Application: 06/230,382 →
Protective Integrated Circuit Device Utilizing Back-to-Back Zener Diodes
Patent: 4,405,933 →
Application: 06/231,288 →
Ttl to Cmos Interface Circuit
Patent: 4,380,710 →
Application: 06/231,671 →
Cmos Amplifier
Patent: 4,446,444 →
Application: 06/231,672 →
Precharge with Power Conservation
Patent: 4,405,996 →
Application: 06/232,303 →
Pulse Generating Circuit Using Current Source
Patent: 4,386,284 →
Application: 06/232,360 →
Reversibly Programmable Polycrystalline Silicon Memory Element
Patent: 4,420,766 →
Application: 06/232,520 →
Transistor with Integrated Diode and Resistor
Patent: 4,398,206 →
Application: 06/233,488 →
Vertical Mosfet with an Aligned Gate Electrode and Aligned Drain Shield Electrode
Patent: 4,455,565 →
Application: 06/234,834 →
Transistor Having Improved Turn-Off Time and Second Breakdown Characteristics with Bi-Level Emitter Structure
Patent: 4,345,266 →
Application: 06/236,220 →
Method for Improving Adhesion of Metal Film on a Dielectric Surface
Patent: 4,404,235 →
Application: 06/237,415 →
Over-Current Protection Circuits for Power Transistors
Patent: 4,321,648 →
Application: 06/237,872 →
Method of Restoring Semiconductor Device Performance
Patent: 4,341,594 →
Application: 06/238,726 →
Crystal Seed Holder Assembly
Patent: 4,348,365 →
Application: 06/242,046 →
Partially Devitrified Porcelain Containing Bao. 2MGO.2SIO2.,and 2MGO. B2O3 Crystalline Phases Obtained from Alkali Metal Free Divalent Metal Oxide Borosilicate Glass
Patent: 4,355,114 →
Application: 06/242,418 →
Integrated Ram/Earom Memory System
Patent: 4,402,065 →
Application: 06/242,658 →
Silicon Melting Crucible
Patent: 4,356,152 →
Application: 06/243,441 →
Positive Radiation Sensitive Resist Terpolymers
Patent: 4,355,094 →
Application: 06/244,104 →
Alignment-Enhancing Feed-Through Conductors for Stackable Silicon-on- Sapphire Wafers
Patent: 4,394,712 →
Application: 06/244,854 →
Method for Forming a Narrow Thin Film Line
Patent: 4,324,814 →
Application: 06/245,589 →
Thin Film Binary Metallic Eutectics
Patent: 4,500,609 →
Application: 06/245,764 →
Operational Amplifier Employing Complementary Field-Effect Transistors
Patent: 4,377,789 →
Application: 06/246,027 →
Method of Depositing a Refractory Metal on a Semiconductor Substrate
Patent: 4,349,408 →
Application: 06/248,038 →
Method of Passivating a Semiconductor Device with a Multi-Layer Passivant System by Thermally Growing a Layer of Oxide on an Oxygen Doped Polycrystalline Silicon Layer
Patent: 4,344,985 →
Application: 06/248,208 →
Integrated Circuit Protection Device
Patent: 4,400,711 →
Application: 06/249,612 →
Method of Forming a Conductor Pattern Including Fine Conductor Runs on a Ceramic Substrate
Patent: 4,413,766 →
Application: 06/250,992 →
Process for X-Ray Microlithography Using Thin Film Eutectic Masks
Patent: 4,349,621 →
Application: 06/253,985 →
Blister-Free Direct Bonding of Metals to Ceramics and Metals
Patent: 4,409,278 →
Application: 06/254,840 →
Composite Circuit for Power Semiconductor Switching
Patent: 4,663,547 →
Application: 06/257,080 →
Operational Amplifier with Feed-Forward Compensation Circuit
Patent: 4,410,857 →
Application: 06/258,406 →
Radiation Shadow Projection Exposure System
Patent: 4,348,105 →
Application: 06/259,362 →
Simultaneously Doped Light-Emitting Diode
Application: 06/261,584 →
Method of Forming Self-Aligned Contact in Semiconductor Devices
Patent: 4,353,159 →
Application: 06/262,620 →
Method of Forming a Layer of Polymethyl Methacrylate on a Surface of Silicon Dioxide
Patent: 4,352,839 →
Application: 06/267,101 →
Device for Multisample Infrared Analysis of Materials in Microgram Quantity
Patent: 4,399,361 →
Application: 06/268,283 →
Multi-Layer Passivant System
Patent: 4,420,765 →
Application: 06/268,284 →
Chopper-Stabilized Amplifier
Patent: 4,423,385 →
Application: 06/272,362 →
Method for Enhancing Electron Mobility in Gaas
Patent: 4,383,869 →
Application: 06/273,303 →
Method of Forming Tapered Contact Holes for Integrated Circuit Devices
Patent: 4,363,830 →
Application: 06/276,012 →
Irradiation Apparatus Utilizing Linear Radiation Sources
Patent: 4,415,955 →
Application: 06/276,137 →
Optical Measurements of Fine Line Parameters in Integrated Circuit Processes
Patent: 4,408,884 →
Application: 06/278,448 →
Time-Division Multiplex Serial Loop
Patent: 4,389,721 →
Application: 06/278,990 →
Crossover Dielectric Inks
Patent: 4,369,254 →
Application: 06/280,916 →
Conductor Inks
Patent: 4,376,725 →
Application: 06/280,917 →
Overglaze Inks
Patent: 4,377,642 →
Application: 06/280,920 →
Indium Oxide Resistor Inks
Patent: 4,380,750 →
Application: 06/280,934 →
Low Value Resistor Inks
Patent: 4,379,195 →
Application: 06/280,937 →
Method of Making Electrically Programmable Control Gate Injected Floating Gate Solid State Memory Transistor
Patent: 4,332,077 →
Application: 06/284,106 →
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Method for Determining Oxygen Content in Semiconductor Material
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Power Efficient Ttl Buffer for Driving Large Capacitive Loads
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Single Chip Microcomputer with External Decoder and Memory and in- Ternal Logic for Disabling the Rom and Felocating the Ram
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Method of Patterning a Thick Resist Layer of Polymeric Plastic
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Porcelain Coated Metal Boards Having Interconnections Between the Face and Reverse Surfaces Thereof
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Method of Making Integrated Circuits Utilizing Ion Implantation and Selective Epitaxial Growth
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Transparent Conductive Film Having Areas of High and Low Resistivity
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Electromagnetic Radiation Annealing of Semiconductor Material
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Aqueous Developable Poly(Olefin Sulfone) Terpolymers
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Plasma Etching of Aluminum
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Composite Conductive Structures and Method of Making Same
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Mosfet-Gated Bipolar Transistors and Thyristors with Both Turn-on and Turn-Off Capability Having Single-Polarity Gate Input Signal
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Dynamic Shift Register Utilizing Cmos Dual Gate Transistors
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Crossover Dielectric Inks Used in Forming a Multilayer Electrical Circuit
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Doped-Oxide Diffusion of Phosphorus Using Borophosphosilicate Glass
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Low Temperature Elevated Pressure Glass Flow/Re-Flow Process
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Insulating Film Having Electrically Conducting Portions
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Electrical Assembly Including a Conductor Pattern Bonded to a Non- Metallic Substrate and Method of Fabricating Such Assembly
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Low Resistance Contact for High Density Integrated Circuit
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Slic Ii - Common Mode Current Rejection
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Overglaze Inks
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Positive Radiation Sensitive Resist Terpolymer from Omega Alkynoic Acid
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System for Polynomial Division Self-Testing of Digital Networks
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Minimal Mask Process for Manufacturing Insulated-Gate Semiconductor Devices with Integral Shorts
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Cache Memory Flush Scheme
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Protection Circuit for Integrated Circuit Devices
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Voltage Equalizer Bridge
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High Speed Charge Balancing Comparator
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Monitor for Impurity Levels in Aluminum Deposition
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Automatic Liquid Dispensing Apparatus for Spinning Surface of Uniform Thickness
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Method to Determine the Crystalline Properties of an Interface of Two Materials by an Optical Technique
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Dry Developable Positive Photoresists
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Coincident Pulse Cancelling Circuit
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Level Shift Interface Circuit
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I2L Structure and Fabrication Process Compatible with High Voltage Bipolar Transistors
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Formant-Based Speech Synthesizer
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Electrically Alterable, Nonvolatile Floating Gate Memory Device
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Semiconductor Device with Internal Gettering Region
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Transient Signal Suppression Circuit
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Method of Making an Integrated Circuit Incorporating Low Voltage and Hugh Voltage Semiconductor Devices
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Method of Forming Metal Lines
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Digitally Switched Analog Signal Conditioner
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A. C. Testing of Logic Arrays
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Normally-Off Semiconductor Device with Low on Resistance and Circuit Analogue
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Power Chip Package
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Air-Fireable Thick Film Inks
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Method of Making a Semiconductor Device to Improve Conductivity of Amorphous Silicon Films
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Deposition of Silicon Dioxide
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Indium Oxide Resistor Inks
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Integrated Circuit Switch Using Stacked Scrs
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Arithmetic Logic Unit
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Five-Transistor Static Memory Cell Implemental in Cmos/Bulk
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Method of Forming a Self Aligned Aluminum Polycrystalline Silicon Line
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Process for Fabrication of High-Speed Radiation Hard Bipolar Semiconductor Devices
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Processes and Gas Mixtures for the Reactive Ion Etching of Aluminum and Aluminum Alloys
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Normally-Off, Gate-Controlled Electrical Circuit with Low On-Resistance
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Apparatus for Spraying a Liquid on a Spinning Surface
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Address Decoder
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Chemical Deposition Termination
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Cmos D-Type Latch Employing Six Transistors and Four Diodes
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Cmos Latch Cell Including Five Transistors, and Static Flip-Flops Employing the Cell
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Method for Mounting a Sapphire Chip on a Metal Base and Article Produced Thereby
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Programmable Logic Gates and Networks
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Insulated-Gate Semiconductor Device with Low On-Resistance
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Reverse Etching of Chromium
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Lid Latching Apparatus
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Method of Forming Refractory Metal Conductors of Low Resistivity
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Controlled Current Limiter
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Amplifying Gate Thyristor Having High Gate Sensitivity and High Dv/Dt Rating
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Memory System
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Binarily Weighted D to a Converter Ladder with Inherently Reduced Ladder Switching Noise
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Semiconductor Device with Built-Up Low Resistance Contact
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Method for Manufacturing Insulated-Gate Semiconductor Devices with Integral Shorts
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Cmos Structure Incorporating Vertical Igfets
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High Voltage Current Mirror
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Reduction of Series Propagation Delay and Impedance
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Power Switched Logic Gates
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Linear Sense Amplifier
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Process for Radiation Free Electron Beam Deposition
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Pinch Rectifier
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High Voltage Integrated Circuits
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Method of Fabricating Low Noise Reference Diodes and Transistors
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Dielectric Isolation Fabrication for Laser Trimming
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Method for Grounding a Pellet Support Pad in an Integrated Circuit Device
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Electrically Alterable Programmable Nonvolatile Floating Gate Memory Device
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Speech Data Econding Scheme
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Method of Determining Position on a Wafer
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Priority Encoded Spare Element Decoder
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Fiber Optics Transducers for Sensing Parameter Magnitude
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Method and Apparatus for Implanation of Doubly-Charged Ions
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Sipos Deposition Method
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Interconnection Structure for Polycrstalline Silicon Resistor and Methods of Making Same
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Field Effect Semiconductor Devices and Method of Making Same
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Fast Switching Circuit
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Local Oxidation of Silicon Substrate Using Lpcvd Silicon Nitride
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Multiple Connection Bond Pad for an Integrated Circuit Device and Method of Making Same
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Surface Preparation for Determining Diffusion Length by the Surface Photovoltage Method
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Method for Revealing Semiconductor Surface Damage Using Surface Damage Using Surface Photovoltage (Spv) Measurements
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Method of Forming Semiconductor Contacts by Implanting Ions of Neutral Species at the Interfacial Region
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Method for Growing Monocrystalline Silicon on a Mask Layer
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Bias Network Having One Mode for Producing a Regulated Output
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Method for Producing Eutectics as Thin Films Using a Quartz Lamp as a Heat Source in a Line Heater
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Method for Producing Eutectics as Thin Films Using a Line Heater
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Method for Producing Eutectics as Thin Films Using an Arc Lamp as a Heat Source in a Line Heater
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Method for Producing Eutectics as Thin Films Using a Laser Device as a Heat Source
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Diffraction Grating Wire Arrays in Parallel
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A Diffraction Grating Wire Arrays in Series
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Eutectic Fine Wire Arrays
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Distributor Tube for Cvd Reactor
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Method of Fabricating High Speed Cmos Devices
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High Density Programmable Memory Array
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Electrical Connector
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Ttl Circuit with a Clamping Transistor for Speedy Turn- Off of Output Transistor
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Fatterning of Submicrometer Metal Silicide Structures
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Selective Semiconductor Coating and Protective Mask Therefor
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Preparation of Organic Layers for Oxygen Etching
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Process for Minimizing Boron Depletion in N-Channel Fet at the Silicon-Silicon Oxide Interface
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Method of Making an Insulated-Gate Semiconductor Device with Improved Shorting Region
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Auto Ranging Counter
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Cmos Backup Power Switching Circuit
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Dielectric Layers in Multilayer Refractory Metallization Structure
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Regulator for Bias Current of Semiconductor Laser Diode
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Analog to Digital Converter with Parallel and Successive Approximation Stages
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Flash Analog to Digital Converter
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Method of Making Vertical Mosfet with Reduced Bipolar Effects
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Method of Forming Self-Aligned Contact Openings
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Method Using Surface Photovoltage (Spv) Measurements for Revealing Heavy Metal Contamination of Semiconductor Material
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Lpcvd Deposition of Tantalum Silicide
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Solid State Zone Recrystallization of Semiconductor Material on an Insulator
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High Density Packaging Technique for Electronic Systems
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Circuit for Self-Commutated Turn-Off of Latched Devices, Such as of the Insulated-Gate Transistor/Rectifier Type
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Ohmic Contacts and Interconnects to Silicon and Method of Making Same
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Current Compensation for Logic Gates
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Method of Fabricating an Isolated Gate Jfet
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Power Down Sensor
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Deep Ultraviolet (Duv) Flood Exposure System
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Deep Ultraviolet (Duv) Flood Exposure System
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Mosfet with Reduced Bipolar Effects
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Method for Growing Monocrystalline Silicon Through Mask Layer
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Switching Circuit
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Laser Trimming of Resistors Over Dielectrically Isolated Islands
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Universal Interface Circuit for Microprocessor Peripherals
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Polysilicon Thin Films of Improved Electrical Uniformity
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Priority Arbitration Logic for a Multi-Master Bus System
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Analog-To-Digital Converters with Virtual Integration
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Efficiency Switching Voltage Converter System
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Grain-Driven Zone-Melting of Silicon Films on Insulating Substrates
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Tape Automated Manufacture of Power Semiconductor Devices
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Grey Code Dac Ladder
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Current to Voltage Interface
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Voltage Level Sensing Circuit
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Circuit for Increasing Voltage Gain
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Diode Structure
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Electrically Alterable, Nonvolatile Floating Gate Memory Device
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Ion-Implantation of Phosphorous, Arsenic or Boron by Pre-Amorphizing with Fluorine Ions
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Deposition of Borophosphosilicate Glass
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Semiconductor Structure for Electric Field Distribution
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Implant Mask Reversal Process
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Reusable Centrifuge Fixture and Methods of Making and Using Same
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High-Speed Output Driver
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Method of Making Vertical Channel Field Controlled Device Employing a Recessed Gate Structure
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Forming Electrical Conductors in Long Microdiameter Holes
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Method for Nucleating and Growing Tungsten Films
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Neutralization of Acceptor Levels in Silicon by Atomic Hydrogen
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Anisotropic Etching of Aluminum
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Gate Shield Structure for Power Mos Device
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Gray Code Counter
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Fabrication of Integrated Circuit with Complementary, Dielectrically- Isolated, High Voltage Semiconductor Devices
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Enhancing the Selectivity of Tungsten Deposition on Conductor and Semiconductor Surfaces
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Differential Input Stage for the Realization of Low Noise and High Precision Bipolar Transistor Amplifiers
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Frequency Response Amplifier
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Method for Selective Deposition of Tungsten on Silicon
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Programmable Current Mirror
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Anti-Vibration System
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Cmos Power-Up Reset Circuit for Gate Arrays and Standard Cells
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High-Speed Voltage Level Shift Circuit
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Monolithic Transient Protector
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Redundant Row Decoding for Programmable Devices
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Electrochemical Dielectric Isolation Technique
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Power Semiconductor Devices with Increased Turn-Off Current Ratings and Limited Current Density in Peripheral Portions
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Bit-Line Pull-Up Circuit
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Normally-Off Semiconductor Device with Low on Resistance and Circuit Analogue
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Multiplexed-Access Scan Testable Integrated Circuit
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Low Temperature Growth of Silicon Dioxide on Silicon
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Method for Making Vertical Channel Field Controlled Device Employing a Recessed Gate Structure
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Methods of Making Self-Aligned Power Mosfet with Integral Source-Base Short
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Alignment Target Image Enhancement for Microlithography Process
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Method for Forming Uniformly Thick Selective Epitaxial Silicon
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Input Signal Conditioning Circuit
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Method of Making High Breakdown Voltage Semiconductor Device
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Bidirectional, High-Speed Power Mosfet Devices with Deep Level Recombination Centers in Base Region
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Reactive Sputter Etching of Metal Slicide Structures
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Conductivity Modulated Semiconductor Structure
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Vertical Mosfet with Diminished Bipolar Effects
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Delay Circuit for a Real Time Clock
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Circuit and Structure for Protecting Integrated Circuits from Destructive Transient Voltages
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Formation of Conductive Lines
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Method of Making an Integrated Circuit
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Two-Layer Negative Resist
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Crossunders for High Density Sos Integrated Circuits
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Nonplanar Ion- Sensitive Field - Effect Transistor Devices
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Flow Through Isfet and Method of Forming
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Electrically Erasable Fused Programmable Logic Array
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Method for Making Semiconductor Device with Integral Fuse
Patent: 4,598,462 →
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Method for Making Silicon Wafers
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Application: 06/717,364 →
Analog-To-Digital Converter with Scaling of Input Signal
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Electronic Static Switched-Latch Frequency Divider Circuit with Odd Number Counting Capabilty
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Non-Restricted Level Shifter
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Subcollector for Oxide and Junction Isolated Ic's
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Comprehensive Semiconductor Test Structure
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Graded Extended Drain Concept for Reduced Hot Electron Effect
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Hybrid Extended Drain Concept for Reduced Hot Electron Effect
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Simultaneous Plasma Sculpturing and Dual Tapered Aperture Etch
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Photoresist Tapering Process
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Stress Free Dielectric Isolation Technology
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Precision Setting of the Bias Point of an Amplifying Means
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Power Supply Switching Circuit
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Ttl Compatible Cmos Input Buffer
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Diamond-Like Film
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Method for Thinning Silicon
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Method of Laser Soldering
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Zener Diode Structure
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Bit Addressable Programming Arrangement
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Dual Inverse Zener Diode with Buried Junctions
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Absorptive Layer for Optical Lithography
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Protection Circuit for Integrated Circuit Devices
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Pulsed Linear Integrated Circuit Tester
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Programmable Interface
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In-Situ Cleaned Ohmic Contacts
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Process of Using Absorptive Layer in Optical Lithography with Over- Lying Photoresist Layer to Form Relief Pattern on Substrate
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Vertical Igfet with Internal Gate and Method for Making Same
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Direct Coupled Swithcing Power Supply with Gto Scr Switching Element
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Clock Synchronization Circuit for a Computer Timer
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Fast Ternary (Gainas) Logic Gate Device
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Automatic Pin Extraction Apparatus for Integrated Circuit Tube
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Asymmetrical Field Controlled Thyristor
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Pulse Position Modulated Regulation for Power Supplies
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Method of Forming Multi-Level Metallization
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Fuse Programmable Dc Level Generator
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Method of Making a Mos Field Effect Transistor in an Integrated Circuit
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Absorptive Planarizing Layer for Optical Lithography
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Power Field-Effect Transition Structures
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Method of Ensuring Adhesion of Chemically Vapor Deposited Oxide to Gold Integrated Circuit Interconnect Lines
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Method for Successive Approximation a/D Conversion
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Electrodeposition of Submicrometer Metallic Interconnect for Integrated Circuits
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Method of Selectively Soldering the Underside of a Substrate Having Leads
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Method for Fabricating a Radiation Hardened Oxide Having Two Portions
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Method for Fabricating a Radiation Hardened Oxide Having Structural Damage
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Ttl Compatible Input Buffer
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Method for Preventing Arcing in a Device During Ion-Implantation
Patent: 4,595,837 →
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Ic Which Eliminates Support Bias Influence on Dielectrically Isolated Components
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Method of Making Stabilized Silicon-on-Insulator Field-Effect Transistors Having 100 Oriented Side and Top Surfaces
Patent: 4,662,059 →
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Programmable Array Logic with Shared Product Terms
Patent: 4,644,191 →
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Programmable Array Logic with Shared Product Terms and J-K Registered Outputs
Patent: 4,644,192 →
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Profile Control of Boron Implant
Patent: 4,637,836 →
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Silicon-On-Sapphire Integrated Circuit and Method of Making the Same
Patent: 4,751,554 →
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Digital Timing System
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Insulated Gate Device
Patent: 4,809,045 →
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Insulated Gate Device
Patent: 4,682,195 →
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Zener Structures with Connections to Buried Layer
Patent: 4,652,895 →
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Memory Cell with Diodes Providing Radiation Hardness
Patent: 4,725,875 →
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Front End of an Operational Amplifier
Patent: 4,636,744 →
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Front End Stage of an Operational Amplifier
Patent: 4,636,743 →
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Process Using Tungsten for Multilevel Metallization
Patent: 4,650,696 →
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Optical Profilometer for Steep Surface Contours with Significant Surface Tilt
Patent: 4,579,454 →
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Method for Increasing the Switching Speed of a Semiconductor Device by Neutron Irradiation
Patent: 4,684,413 →
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Dual Slope Converter with Large Apparent Integrator Swing
Patent: 4,656,459 →
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Dual Slope Analog-T0-Digital Converter with Automatic, Short Cycle Range Determination
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Internally Synchronous Matrix Structure for Use in Externally Asynchronous Programmable Devices
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Fabrication of Vertical Npn and Pnp Bipolar Transistors in Monolithic Substrate
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Programming Arrangement for Programmable Devices
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Auxiliary Word Line Driver for Effectively Controlling Programmability of Fusible Links
Patent: 4,734,886 →
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High Voltage Semiconductor Devices Electrically Isolated from an Integrated Circuit Substrate
Patent: 4,661,838 →
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Refractory Metal Capacitor Structures, Particularly for Analog Integrated Circuit Devices
Patent: 4,638,400 →
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Apparatus for Holding a Part in a Wave Soldering Machine
Patent: 4,614,294 →
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Spin-Coating Procedure
Patent: 4,741,926 →
Application: 06/792,535 →
Lift-Off Technique for Producing Metal Pattern Using Single Photo- Resist Processing and Oblique Angle Metal Deposition
Patent: 4,687,730 →
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Variable Wavelength Optical Alignment System
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Switchable Oscillator Circuit
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System for Determining Time Duration of Angular Rotation
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Comparator Input Stage for Interface with Signal Current
Patent: 4,682,059 →
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Video Coupler Device
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Method to Inhibit Autodoping in Epitaxial Layers from Heavily Doped Substrates in Cvd Processing
Patent: 4,661,199 →
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Dense, Reduced Leakage Cmos Structure
Patent: 4,720,739 →
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Conveyor for Vapor Phase Reflow System
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Integrated Circuit Device Having Slanted Peripheral Circuits
Patent: 4,789,889 →
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Treatment of Planarizing Layer in Multilayer Electron Beam Resist
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Method of Depositing Uniformly Thick Selective Epitaxial Silicon
Patent: 4,698,316 →
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Method and Apparatus for Forming Large Area High Resolution Patterns
Patent: 4,668,080 →
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Lateral Insulated Gate Bipolar Transistors with Improbed Latch-Up Immunity
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Integrated Circuit for Controlling Power Converter by Frequency Modulation and Pulse Width Modulation
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Current Limited Insulated Gate Device
Patent: 4,641,162 →
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Semiconductor Wafer with an Electrically-Isolated Semiconductor Device
Patent: 4,862,242 →
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Level Shift Circuit Including Source Follower Output
Patent: 4,695,744 →
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Technique for Increasing Gate-Drain Breakdown Voltage of Ion-Implanted Jfet
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Control of Signal Transmission
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Multi-Driver Integrated Circuit
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Apparatus and Method for Producing Ions
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Apparatus and Method for Producing Ions
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Esd Protection Transistors
Patent: 4,760,433 →
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Non-Contact I/O Signal Transmission in Integrated Circuit Packaging
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Via Metallization Using Metal Fillets
Patent: 4,666,737 →
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Multilayer Interconnect and Method of Forming Same
Patent: 4,926,236 →
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Recessed Oxide Method for Making a Silicon-on-Insulator Substrate
Patent: 4,704,186 →
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High Voltage Lateral Mos Structure with Depleted Top Gate Region
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Orthogonal Bipolar Transistor
Patent: 4,792,837 →
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Bipolar Transistor with Transient Suppressor
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Overvoltage Comparator
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Comparator Circuit
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Cfet Inverter Having Equal Output Signal Rise and Fall Times by Adjustment of the Pull--- Up and -Down Transconductances
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Method for Gate Electrode Fabrication and Symmetrical and Non-Symmetrical Self-Aligned Inlay Transistors Made Therefrom
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Technique for Elimination of Polysilicon Stringers in Direct Moat Field Oxide Structure
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Test Circuitry for Testing Fuse Link Programmable Memory Devices
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Test Enabling Circuit for Enabling Overhead Test Circuitry in Programmable Devices
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Pulse Electro-Magnetic Field Therapy Device with Auto Bias Circuit
Patent: 4,674,482 →
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Method for Producing High-Aspect Ratio Hollow Diffused Regions in a Semiconductor Body and Diode Produced Thereby
Patent: 4,720,308 →
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Unframed via Interconnection with Dielectric Etch Stop
Patent: 4,767,724 →
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Semiconductor Chip Packages Having Solder Layers of Enhanced Durability
Patent: 4,769,744 →
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Method of Making a Floating Gate Memory Cell
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Epitaxial Metal Silicide Layers
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Self-Aligned Inlay Transistor with or Without Source and Drain Self-Aligned Metallization Extensions
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Method of Fabricating Gold Bumps on Ic's and Power Chips
Patent: 4,750,666 →
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Method of Forming a Semiconductor Structure
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Silicon-On-Sapphire Integrated Circuits
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Method for Forming Dielectrically Isolated Pmos, Nmos, Pnp and Npn Transistors on a Silicon Wafer
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Hybrid Extended Drain Concept for Reduced Hot Electron Effect
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Integrated Circuits with Electrically Erasable Electrically Programmable Latch Circuits Therein for Controlling Operation
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Transistor Base Current Regulator
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Method of Making a Silicon-on-Insulator Transistor
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A Method of Fabricating a Substrate for a Semiconductor Chip Package
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Active Area Planarization with Self-Aligned Contacts
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Bidirectional Vertical Power Mos Device and Fabrication Method
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Parallel Processing System Apparatus
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Hermetic Power Chip Packages
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Multiple-Layer, Multiple-Phase Titanium/Nitrogen Adhesion/Diffusion Barrier Layer Structure for Gold-Base Microcircuit Interconnection
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Method of Forming Isolation Regions in a Semiconductor Device
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Article Transfer System
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Passivation with a Low Oxygen Interface
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High Voltage Ic Bipolar Transistors Operable to Bvcbo and Method of Fabrication
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Test Mask for Determining Alignment of an Automatic Ic Mask Testing Apparatus
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High Current Lateral Transistor Structure
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Constant Current Load and Level Shifter Circuitry
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Electroless Nickel Plating Composition and Method
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Cmos Input Level Shifting Buffer Circuit
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Method and Apparatus for Improved Metal-Insulator-Semiconductor Device Operation
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Method for Determining Structural Defects in Semiconductor Wafers by Ultrasonic Microscopy
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Illuminator for Visual Inspection of Curved Specular Surfaces
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Alternating Current Power Loss Detector
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Power Semiconductor Device with Main Current Section and Emulation Current Section
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Arc Gap for Integrated Circuits
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Low Noise Current Spectral Density Input Bias Current Cancellation Scheme
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Low Power Sense Amplifier
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Tape Automated Manufacture of Power Semiconductor Devices
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Memory Cell Circuit Having Radiation Hardness
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Logic State Transition Detection Circuit for Cmos Devices
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Thermally Coupled Information Transmission Across Electrical Isolation Boundaries
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Radiation Hard Memory Cell Circuit with High Inverter Impedance Ratio
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Radiation Hard Memory Cell Structure with Drain Shielding
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Process of Forming a Resist Structure on Substrate Having Topo- Graphical Features Using Positive Photoresist Layer and Poly (Vinlypyrrolidone) Overlayer
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Digital Multiplier Architecture with Triple Array Summation of Partial Products
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Method of Making Silicon-on-Sapphire Semiconductor Devices
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Method of Forming Tapered Contact Openings
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Igt and Mosfet Devices Having Reduced Channel Width
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Esd Protection Network for Igfet Circuits with Scr Prevention Guard Rings
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Integrated Lateral Pnp Transistor and Current Limiting Resistor
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Efficiency Switching Voltage Converter System
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Alignment Key and Method of Making the Same
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Reduced Parallel Exclusive or and Exclusive nor Gate
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Stethoscope Having Pseudostereophonic Binaural Enhancement
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Front End Stage of an Operational Amplifier
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Dielectric for Laser Trimming
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Bidirectional Vertical Power Mos Device and Fabrication Method
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Constant Ratio, Size Insensitive, Capacitor Structure
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Method of Fabricating a Twin Tub Cmos Device
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Decoder Circuitry with Reduced Number Inverters and Bus Lines
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Minimal Mask Process for Fabricating a Lateral Insulated Gate Semiconductor Device
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Method of Enhancing Silicon Etching Capability of Alkali Hydroxide Through the Addition of Positive Valence Impurity Ions
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Memory Cell for a Dense Eprom
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Regulator Circuit for Conventing Alternating Input to a Constant Direct Output
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Fabrication of Large Power Semiconductor Composite by Wafer Interconnection of Individual Devices
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Technique for Forming Electric Field Shielding Layer in Oxygen- Implanted Silicon Substrate
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Fabrication of Vertical Npn and Pnp Bipolar Transistors in Monolithic Substrate
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Process for Performing Variable Selectivity Polysilicon Etch
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Ratioed Power on Reset Circuit
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Lateral Charge Control Semiconductor Device and Method of Fabrication
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Mosfet Structure with Substrate Coupled Source
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Apparatus and Method for Maintaining a Uniform Etching Solution Composition
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Method of Forming a Patterned Glass Layer Over the Surface of a Substrate
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Programmable Logic Device with Programmable Signal Inhibition and Inversion Means
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Vertical Mosfet with Reduced Bipolar Effects
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Capacitor and Method for Making Same with High Yield
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Semiconductor Device with Source and Drain Depth Extenders and a Method of Making the Same
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Method for Forming Planarized Interconnect Level Using Selective Deposition and Ion Implantation
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Insulated Gate Semiconductor Device with Extra Short Grid and Method of Fabrication
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Double Level Conductor Structure
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Process for the Fabrication of a Vertical Contact
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Fast Voltage Reference Stabilization Circuit
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Isolation for Transistor Devices Having a Pilot Structure
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Dielectrically Isolated Pmos, Nmos, Pnp and Npn Transistors on a Silicon Wafer
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Vertical Double Diffused Metal Oxide Semiconductor Vdmos Device with Increased Safe Operating Area and Method
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Vertical Double Diffused Metal Oxide Semiconductor (Vdmos) Device Including High Voltage Junction Exhibiting Increased Safe Operating Area
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Semiconductor Device Having Turn-on and Turn-Off Capabilities
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Area Feature Sorting Mechanism for Neighborhood-Based Proximity Correction in Lithography Processing of Integrated Circuit Patterns
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Switched Capacitor Filter for Use with a Digital-to-Analog (D/a) Converter
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Semiconductor Device Having Rapid Removal of Majority Carriers from an Active Base Region Thereof at Device Turn-Off and Method of Fabricating This Device
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Optical Reflectance Method of Examining a Simox Article
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Using a Rapid Thermal Process for Manufacturing a Wafer Bonded Soi Semiconductor
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Integrated Circuit for Controlling Power Converter by Frequency Modulation and Pulse Width Modulation
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Method of Ensuring Adhesion of Chemically Vapor Deposited Oxide to Gold Integrated Circuit Interconnect Lines
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Large Signal Output Current Enhancement for a Differential Pair
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Activation of Refractory Metal Surfaces for Electroless Plating
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Structure for High Breakdown Pn Diode with Relatively High Surface Doping
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Semiconductor Device That Minimizes the Leakage Currents Associated with the Parasitic Edge Transistors and a Method of Making the Same
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Edgeless Semiconductor Device
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Treatment of Planarizing Layer in Multilayer Electron Beam Resist
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Bonding Technique to Join Two or More Silicon Wafers
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Adjustable Windage Method and Mask for Correction of Proximity Effect in Submicron Photolithography
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Monolithically Integrated Semiconductor Device and Process for Fabrication
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Performing Binary Multiplication Using Minimal Path Algorithm
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Monolithically Integrated Insulated Gate Semiconductor Device
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Monolithically Integrated Lateral Insulated Gate Semiconductor Device
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Monolithically Integrated Semiconductor Device Having Bidirectional Conducting Capability and Method of Fabrication
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Method of Making Integrated Circuit with Pair of Mos Field Effect Transistors Sharing Common Source/Drain Region
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Multiple Layer, Tungsten/Titanium/Titanium Nitride Adhesion/Diffusion Barrier Layer Structure for Gold-Base Microcircuit Interconnection
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Zener Referenced Voltage Circuit
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Self-Aligned Contact for Mos Processing
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Self-Aligned Barrier Metal and Oxidation Mask Method
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Method for Fabricating a Self-Aligned Lightly Doped Drain Semiconductor Device with Silicide
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Self-Aligned Contacts for Bipolar Process
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Method of Making a Power Ic Structure with Enhancement and/or Cmos Logic
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Dielectric Isolation Process Using Double Wafer Bonding
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Metal Oxide Semiconductor Gated Turn Off Thyristor
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Method of Laser Soldering
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Buried Lateral Diode and Method for Making Same
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Controlled Switching Cmos Output Buffer
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Semiconductor Device and Method of Fabrication
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Static Cmos Programmable Logic Array
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Photolithography Over Reflective Substrates Comprising a Titanium Nitride Layer
Patent: 4,810,619 →
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Technique for Elimination of Polysilicon Stringers in Direct Moat Field Oxide Structure
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Timing and Control Circuitry for Flash Analog to Digital Converters with Dynamic Encoders
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Lateral Metal-Oxide-Semiconductor Controlled Triacs
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Double Epitaxial Method of Fabricating Semiconductor Devices on Bonded Wafers
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Low Reflectance Conductor in an Integrated Circuit
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Insulated-Gate Semiconductor Device with Improved Base-to-Source Electrode Short and Method of Fabricating Said Short
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Chip Carrier Soldering Pallet
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Method of Filling Interlevel Dielectric via or Contact Holes in Multilevel Vlsi Metallization Structures
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Impedance Transforming Circuit for Multibit Parallel Digital Circuits
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Digital to Analog Converter with Switch Function Compensation
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Cell Based Alu with Tree Structured Carry, Inverting Logic and Balanced Loading
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Determination of Substrate Temperature Used During Oxygen Implantation of Simox Wafer
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Conductivity-Modulated Fet with Improved Pinch Off-Ron Performance
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Operational Amplifier Having Low Dc Current Input Circuit
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Cmos Voltage Divider Circuits
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Method of Making Mo/Tiw or W/Tiw Ohmic Contacts to Silicon Same
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Structure and Method for Preventing Latch-Up in Integrated Circuits
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Chip Carrier and Method of Fabrication
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Cell Based Adder with Tree Structured Carry, Inverting Logic and Balanced Loading
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High Voltage Ic Bipolar Transistors Operable to Bvcbo and Method of Fabrication
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Speed Enhancement for Multipliers Using Minimal Path Algorithm
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Dense Eprom Having Serially Coupled Floating Gate Transistors
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High Temperature Annealing to Improve Simox Characteristics
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Method of Packaging a Non-Contact I/O Signal Transmission Integrated Circuit
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Ion Implantation Method and Apparatus
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Analog to Digital Converter with Integral Linearity Error Compensation and Method of Operation
Patent: 4,924,225 →
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Metallization Contact System for Large Scale Integrated Circuits
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Ion Implanted Jfet with Self-Aligned Source and Drain
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High Voltage Integrated Circuit Devices Electrically Isolated from an Integrated Circuit Substrate
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Soft Start Solid State Switch
Patent: 5,015,921 →
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Isolated Gate Mesfet and Method of Making and Trimming
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Gate Enhanced Rectifier
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High Speed Apparatus for a Single Latch Flash Analog-to-Digital Converter
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Structure for a Complementary-Symmetry Comfet Pair
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Fabrication Method and Structure for Field Isolation in Field Effect Transistors on Integrated Circuit Chips
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Decoder Error Prevention Apparatus for Use in Flash Analog-to-Digital Converters
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Self-Characterizing Analog-to-Digital Converter
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Truncated Product Partial Canonical Signed Digit Multiplier
Patent: 4,967,388 →
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Simple Automated Discretionary Bonding of Multiple Parallel Elements
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Self-Planarized Gold Interconnect Layer
Patent: 4,970,573 →
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Cell Stack for Variable Digit Width Serial Architecture
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Low Noise, High Frequency Synchronous Rectifier
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Method of Etching Silicon by Enhancing Silicon Etching Capability of Alkalli Hydroxide Through the Addition of Positive Valence Impurity Ions
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Digital Filter Employing Parallel Processing
Patent: 4,947,362 →
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Metal Oxide Semiconductor Gated Turn-Off Thyristor Including a Low Lifetime Region
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Method of Making Symmertical Blocking High Voltage Breakdown Semiconductor Device
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Method and Apparatus for Computing Square Roots of Binary Numbers
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Integrated Circuits Including Photo-Optical Devices and Pressure Transducers and Method of Fabrication
Patent: 4,916,497 →
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Graded Extended Drain Concept for Reduced Hot Electron Effect
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Bipolar Transistor with Field Shields
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Current Compensated Precharged Bus
Patent: 4,857,764 →
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Memory Cell Structure Having Radiation Hardness
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Method of Fabricating Self Aligned Semiconductor Devices
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Power Bipolar Transistor Device with Integral Antisaturation Diode
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Transistor Base Current Compensation Circuitry
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Power Transistor Structure with High Speed Integral Antiparallel Schottky Diode
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Technique for Forming Planarized Gate Structure
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Compensated Current Sensing Circuit
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Protective Clamp for Mos Gated Devices
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Hermetically Sealed Housing
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Complementary Circuit and Structure with Common Substrate
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Self Packaging Chip Mount
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Trench Gate Vcmos
Patent: 4,951,102 →
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Semiconductor Devices Exhibiting Minimum On-Resistance
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Mct Providing Turn-Off Control of Arbitrarily Large Currents
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Method of Making Direct Bonded Wafers Having a Void Free Interface
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Method for Fabricating a Self-Aligned Lightly Doped Drain Semiconductor Device with Silicide
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High Voltage Semiconductor Devices with Reduced On-Resistance
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Insulated Gate Transistor with Vertical Integral Diode and Method of Fabrication
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Radiation Hard Memory Cell Having Monocrystalline and Non-Monocrysta- Lline Inverters
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A Buried Oxide Field Isolation Structure with Composite Dielectric
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Apparatus and Method for Optical Dimension Measurement Using Interference of Scattered Electromagnetic
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High Breakdown Active Device Structure with Low Series Resistance
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Circuit Including a Combined Insulated Gate Bipolar Transistor/Mosfet
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Fast Level Translator Circuit
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High Accuracy Current Source and High Accuracy Transconductance Stage
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Adjustable Windage Method and Mask for Correction of Proximity Effect in Submicron Photolithography
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Method for Forming Complementary Patterns in a Semiconductor Material While Using a Single Masking Step
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Fast Image Processing Accelerator for Real Time Image Processing Applications
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Method of Fabricating a Field Effect Semiconductor Device Having a Self-Aligned Structure
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Transimpedance Focal Plane Processor
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High Accuracy, High Impedance Differential to Single-Ended Current Converter
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Dielectric Isolation for Soi Island Side Wall for Reducing Leakage Current
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Optoelectronic System for Determining Surface Irregularities of a Workpiece Having a Nominally Plane Reflective
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Insulated Gate Bipolar Transistor with Improved Latch-Up Current Level and Safe Operating Area
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Precision Temperature-Stable Current Sources/Sinks
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Method of Fabrication of Isolated Islands for Complementary Bipolar Devices
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Method of Fabricating Back Diffused Bonded Oxide Substrates
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High Speed Low Input Current Voltage Follower Stage
Patent: 4,891,604 →
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Memory with Cache Register Interface Structure
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Dielectric for Laser Trimming
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Method of Making Silicon-on-Insulator Islands
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Method of Making Cmos with Shallow Source and Drain Junctions
Patent: 4,945,070 →
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Low Top Gate Resistance Jfet Structure
Patent: 4,876,579 →
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Voltage Limiter Apparatus with Inherent Level Shifting Employing Mosfets
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High Voltage Mos Structure
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Method of Edge Doping Soi Islands
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Photocurrent Compensation Using Active Devices
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Mos Protection Device
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Ic Which Eliminates Support Bias Influence on Dielectrically Isolated Components
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Method of Self- Packing an Ic Chip
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Voltage Regulator Having Staggered Pole-Zero Compensation Network
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Mos-Pilot Structure for an Insulated Gate Transistor
Patent: 4,980,740 →
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Vertical Contact Structure
Patent: 4,914,501 →
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Forth Specific Language Microprocessor
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Power Field Effect Devices Having Small Cell Size and Low Contact Resistance
Patent: 4,998,151 →
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Back-Sampling Charge Redistribution Analog to Digital Converter
Patent: 4,982,194 →
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Programmable Delay Circuit
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Analog-To-Digital Converter and Method of Use Vitilizin Charge Redistrebution
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Semiconductor Transmission Gate with Capacitance Compensation
Patent: 4,988,902 →
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Unity-Gain Cmos/Sos Zero-Offset Buffer
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Thin Film Resistors and Method of Trimming
Patent: 4,929,923 →
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Method of Making High Breakdown Voltage Semiconductor Device
Patent: 4,927,772 →
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Precise, High Speed Cmos Track (Sample)/Hold Circuits
Patent: 5,036,219 →
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Power Field Effect Devices Having Low Gate Sheet Resistance and Low Ohmic Contact Resistance and Method of Fabrication
Patent: 4,985,740 →
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Full Adder Circuit with Improved Carry and Sum Logic Gates
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Hermetic Package Having a Lead Extending Through an Aperture in the Package Lid and Packaged Semiconductor Chip
Patent: 5,103,290 →
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Bipolar Transistor with High Efficient Emitter
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High Speed, High Precision Operational Amplifier
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High Current Hermetic Package Having a Lead Extending Through the Package Lid and a Packaged Semiconductor Chip
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Hermetic Package and Packaged Semiconductor Chip Having Closely Spaced Leads Extending Through the Package Lid
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High Current Hermetic Package Including an Internal Foil and Having a Lead Extending Through the Package Lid and a Packaged Semiconductor Chip
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A Method of Making Dielectrically Isolated Intergrated Circuits Using Oxygen Implantation and Epitaxial Growth
Patent: 4,929,566 →
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Symmetrical Blocking High Voltage Semiconductor Device and Method of Fabrication
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Method of Making Edge-Connected Integrated Circuit Structure
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Programmable Speed/Power Arrangement for Integrated Devices Having Logic Matrices
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Method for Forming Dielectrically Isolated Transistor
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Simplified Transistor Base Current Compensation Circuitry
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Predrive Circuit Having Level Sensing Control
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Method of Isolating a Top Gate of a Mesfet and the Resulting Device
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Complementary Circuit and Structure with Common Substrate
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Field Controlled Diode (Fcd) Having Mos Trench Gates
Patent: 4,994,883 →
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Radiation Hardened Complementary Transistor Ingrated Circuits
Patent: 5,021,359 →
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Method of Making a Mos Transistor
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Application: 07/418,762 →
Dual Layer Surface Gate Jfet Having Enhanced Gate-Channel Breakdown Voltage
Patent: 5,008,719 →
Application: 07/424,917 →
A-B Buffer Circuit with Ttl Compatible Output Drive
Patent: 5,015,887 →
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Symmetrical Blocking High Voltage Breakdown Semiconductor Device and Method of Fabrication
Patent: 4,999,684 →
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Method and Circuit Arrangement for Providing Programmable Hysteresis to a Differential Comparator
Patent: 5,039,888 →
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Content Addressable Memory Device
Patent: 5,051,949 →
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Symmetrical Variable Impedance Apparatus Employing Mos Transistors
Patent: 5,021,747 →
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High Voltage Integrated Circuits
Patent: 4,958,210 →
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Method of Making a Buried Oxide Field Isolation Structure
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Mo/Ti Contact to Silicon
Patent: 4,981,816 →
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Bias Current Modulation for Differentially Coupled Transistor Circuit
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Power Mosfet Transistor Circuit
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Automatic Esd Protection Device for Semiconductor Packages
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Scr Structure for Fast Turn-on Switching
Patent: 4,979,011 →
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Integrated Circuit with Stacked Mos Field Effect Transistors
Patent: 4,999,691 →
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Enhanced Direct Bond Copper Process and Structure
Patent: 4,996,116 →
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Two Dimensional Hybrid Digital Convolver
Patent: 4,998,288 →
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Cross-Point Switch
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Thin, Dielectrically Isolated Island Resident Transistor Structure Having Low Collector Resistance
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Method of Fabricating Integrated Circuits Including Photo Optical Devices and Pressures Transducers.
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Trench-Resident Interconnect Structure
Patent: 5,070,388 →
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Current Mirror Circuit with Cascoded Transistors
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Turn-Off Circuit for Gate Turn Off Scr
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Variable Length Shift Register
Patent: 5,084,839 →
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Wafer Bonding Using Trapped Oxidizing Vapor
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Digital Signal Processing Address Sequencer
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Manufacturing Ultra-Thin Wafer Using a Handle Wafer
Patent: 5,034,343 →
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Gate Enhanced Rectifier
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Method of Forming a High Voltage Junction in a Dielectrically Isolated Island
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Reduced Contact Resistance on a Slic
Patent: 5,148,475 →
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Low Distortion Sample and Hold Circuit
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Ultra-Thin Circuit Fabrication by Controlled Wafer Debonding
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Digital Decimation Filter
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High Current Hermetic Package
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Adaptive Threshold Suppression of Impulse Noise
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Mesfet for Dielectrically Isolated Integrated Circuits
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Band-Gap Reference
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Trench Gate Vcmos Method of Manufcture
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An Isolated Gate Mesfet and Method of Making and Trimming
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Heat Sink and Multi Mount Pad Lead Frame Package and Method for Electrically Isolating Semiconductor Die(S)
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Hermetically Sealed Die Package with Floating Source
Patent: 5,038,197 →
Application: 07/545,218 →
Ferromagnetic Element with Temperature Regulation
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Application: 07/548,866 →
Sin/Cos Generator Implementation
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Application: 07/561,821 →
Trench Conductor and Crossunder Architecture
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Application: 07/563,276 →
Back-Sampling Analog to Digital Converter
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Method of Making a High Breakdown Active Device Structure with Low Series Resistance
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Application: 07/592,308 →
Fast Turn-Off of Thyristor Structure
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Application: 07/598,165 →
Piso Electrostatic Discharge Protection Device
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Application: 07/601,974 →
Direct Thermocompression Bonding for Thin Electronic Power Chips
Patent: 5,184,206 →
Application: 07/603,495 →
Stacked Configuration for Integrated Circuit Devices
Patent: 5,117,282 →
Application: 07/604,883 →
Integrated Circuits Including Photo-Optical Devices and Pressure Transducers and Method of Fabrication
Patent: 5,070,596 →
Application: 07/606,155 →
Method of Making Silicon Mesfet for Dielectrically Isolated Integrated Circuits
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Power Mosfet
Patent: 5,095,343 →
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Power Mosfet Transistor Circuit with Active Clamp
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Application: 07/609,685 →
Dual Layer Surface Gate Jfet Having Enhanced Gate-Channel Breakdown Voltage
Patent: 5,118,632 →
Application: 07/609,801 →
Method and Apparatus for Testing Lead Bonds and Detecting Failure
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Single Chip 2-D Convolver
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Direct Bonding of Copper to Aluminum Nitride Substrates
Patent: 5,418,002 →
Application: 07/632,876 →
Multiplexed Sigma-Delta a/D Converter
Patent: 5,150,120 →
Application: 07/637,047 →
Photolithographic Formation of Die-to-Package Airbridge in a Semiconductor Device
Patent: 5,198,385 →
Application: 07/640,041 →
A Dielectric Isolation for Soi Island Side Wall for Reducing Leakage Current
Patent: 5,053,353 →
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Single Power Mosfet Ac Power Switch Employing Means for Preventing Conduction of Body Diode
Patent: 5,134,321 →
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Converter Comparartor Cell with Improved Resolution
Patent: 5,140,326 →
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Semiconductor Structure Within Di Islands Having Bottom Projection for Controlling Device Characteristics
Patent: 5,306,944 →
Application: 07/651,327 →
Method of Forming Self-Aligned Top Gate Channel Barrier Region in Ion-Implanted Jfet
Patent: 5,120,669 →
Application: 07/651,460 →
Batch Assembly of High Density Hermetic Packages for Power Semiconductor Chips
Patent: 5,139,972 →
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Level Shift Circuit with Common Mode Rejection
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Application: 07/663,224 →
Semiconductor Device with Improved Turn-Off Capability
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Application: 07/663,780 →
Power-On Reset Circuit
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Application: 07/667,932 →
Manufacturing Ultra-Thin Dielectrically Isolated Wafers
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Application: 07/668,694 →
Method of Isolating a Top Gate of a Mesfet and the Resulting Device
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Power Vdmosfet with Schottky on Lightly Doped Drain of Lateral Driver Fet
Patent: 5,164,802 →
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A Cover with Through Terminals for a Hermetically Sealed Electronic Package
Patent: 5,097,319 →
Application: 07/672,997 →
Graded Collector for Inductive Loads
Patent: 5,311,054 →
Application: 07/674,147 →
Self-Aligned Channel Stop for Trench-Isolated Island
Patent: 5,248,894 →
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Latching Comparator Employing Transfer Gates
Patent: 5,196,737 →
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Method of Laser Trimming
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Application: 07/689,624 →
Voltage Divider and Use as Bias Network for Stacked Transistors
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A Method of Packaging a Semiconductor Chip in a Low Inductance Package
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Full Range Input/Output Comparator
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High Voltage Lateral Semiconductor Device
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Overvoltage Sensor with Hysteresis
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Low Offset Unity Gain Buffer Amplifier
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High Speed Differential Comparator
Patent: 5,332,931 →
Application: 07/720,082 →
Decimation Circuit Employing Multiple Memory Data Shifting Section and Multiple Arithmetic Logic Unit Section
Patent: 5,206,821 →
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High Voltage Protection Using Scrs
Patent: 5,359,211 →
Application: 07/732,475 →
Method of Making Trench Conductor and Crossunder Architecture
Patent: 5,196,373 →
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Buried Zener Diode Having Auxiliary Zener Junction Access Path
Patent: 5,241,213 →
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Integrating a/D Converter with Means for Reducing Rollover Error
Patent: 5,184,128 →
Application: 07/740,700 →
Forth Specific Language Microprocessor
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Two Stage a/D Converter Utilizing Dual Multiplexed Converters with a Common Converter
Patent: 5,138,319 →
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Thin, Dielectrically Isolated Island Resident Transistor Structure Having Low Collector Resistance
Patent: 5,327,006 →
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Method of Forming Hermetic Package Having a Lead Extending Through an Aperture in the Package Lid Packaged Semiconductor Chip
Patent: 5,135,890 →
Application: 07/765,286 →
Resistor Structure and Method of Fabrication
Patent: 5,200,733 →
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Noncanonic Fully Systolic Lms Adaptive Architecture
Patent: 5,450,339 →
Application: 07/774,620 →
Fold and Decimate Filter Architecture
Patent: 5,258,939 →
Application: 07/774,628 →
Direct Bonded Symmetric-Metallic-Laminate/Substrate Structures
Patent: 5,100,740 →
Application: 07/777,495 →
Controlled-Current Lamp Starting Ciruit
Patent: 5,210,471 →
Application: 07/778,660 →
Bimos Current Driver Circuit
Patent: 5,262,689 →
Application: 07/781,626 →
Analog-To-Digital Converter and Method of Fabrication
Patent: 5,369,309 →
Application: 07/785,325 →
Differential Voltage Follower
Patent: 5,382,916 →
Application: 07/785,395 →
Silicon on Diamond Circuit Structure
Application: 07/789,219 →
Power Fet Having Reduced Threshold Voltage
Patent: 5,218,220 →
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Print Band Cleaner
Patent: 5,220,868 →
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Symmetric, High Speed, Voltage Switching Circuit Possessing Reverse Viltage Application Immunity
Patent: 5,302,859 →
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Power Fet with Shielded Channels
Patent: 5,243,211 →
Application: 07/797,054 →
Process for Forming Extremely Thin Edge-Connectable Integrated Circuit Structure
Patent: 5,185,292 →
Application: 07/802,882 →
High Speed Bipolar Digital Logic Gate Architecture
Patent: 5,229,661 →
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Negative Biasing of Isolation Trench Fill to Attract Mobile Positive Ions Away from Bipolar Device Regions
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Field Effect Transistor Controlled Thyristor Having Improved Turn-on Characteristics
Patent: 5,260,590 →
Application: 07/811,999 →
Flash Analog-to-Digital Converter Employing Least Significant Bit- Representative Comparative Reference Voltage
Patent: 5,194,867 →
Application: 07/816,321 →
Bias Current Modulation for Differentially Coupled Transistor Circuit
Patent: 5,214,329 →
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Power Fet with Gate Segments Covering Drain Regions Disposed in a Hexagonal Pattern
Patent: 5,323,036 →
Application: 07/822,732 →
Semiconductor Devices and Methods of Assembly Thereof
Patent: 5,248,901 →
Application: 07/823,343 →
Method of Manufacturing a Multi-Layered I C Packaging Assembly
Patent: 5,228,192 →
Application: 07/825,133 →
Reduced Semiconductor Size Package
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Application: 07/831,252 →
Selective Recrystallization to Reduce P-Channel Transistor Leakage in Silicon-on-Sapphire Cmos Radiation Hardened Integrated Circuits
Patent: 5,298,434 →
Application: 07/832,694 →
Wafer Bonding Process Emplyoing Liquid Oxidant
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Hermetic Ic Package Moisture Tester
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Application: 07/839,426 →
Telephone Subscriber Line Circuit, Components and Methods
Patent: 5,745,563 →
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Method and Device in Which Bottoming of a Well in a Dielectrically Isolated Island Is Assured
Patent: 5,270,569 →
Application: 07/840,548 →
Electrically Programmable Memory Cell
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Application: 07/846,286 →
Semiconductor Device with Improved Turn-Off Capability
Patent: 5,350,935 →
Application: 07/847,789 →
Laser Trimmed Integrated Circuit
Patent: 5,235,205 →
Application: 07/852,541 →
Method of Forming Island with Polysilicon-Filled Trench Isolation
Patent: 5,217,919 →
Application: 07/854,805 →
Soi Cmos Device Having Differentially Doped Body Extension for Providing Improved Backside Leakage Channel Stop
Patent: 5,293,052 →
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Power Driver Circuit
Patent: 5,504,449 →
Application: 07/865,868 →
Integration of High Voltage Lateral Mos Devices in Low Voltage Cmos Architecture Using Cmos-Compatible Process Steps
Patent: 5,322,804 →
Application: 07/882,070 →
Soi Wafer with Sige
Patent: 5,218,213 →
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Method of Fabricating Soi Water with Sige as an Etchback Film in a Besoi Process
Patent: 5,240,876 →
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Precision Voltage Reference Circuit
Patent: 5,300,877 →
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Seu-Immune Latch for Gate Array, Standard Cell, and Other Asic Applications
Patent: 5,311,070 →
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Reduced Temperature Suppression of Volatilization of Photoexcited Halogen Reaction Products from Surface of Silicon Wafer
Patent: 5,352,327 →
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Gas Phase Chemical Reduction of Metallic Branding Layer of Electronic Circuit Package for Deposition of Branding Ink
Patent: 5,279,850 →
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Trench Conductor and Crossunder Architecture
Patent: 5,283,461 →
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Bicmos Devices
Patent: 5,856,695 →
Application: 07/917,635 →
Breakdown Diode Structure
Patent: 5,448,100 →
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Bonded Wafer Processing
Patent: 5,362,667 →
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Formation of Dual Polarity Source/Drain Extensions in Lateral Complementary Channel Mos Architectures
Patent: 5,338,960 →
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Process for Forming Twin Well Cmos Integrated Circuits
Patent: 5,247,199 →
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Quadrature Filter with Real Conversion
Patent: 5,515,402 →
Application: 07/930,072 →
Half-Band Filter and Method
Application: 07/930,167 →
Decimation Filter and Method
Patent: 5,455,782 →
Application: 07/930,169 →
Digital Down Converter and Method
Patent: 5,493,581 →
Application: 07/930,170 →
Current Driver Having Voltage Transition Failure-Based Short Circuit Protecton Circuit
Patent: 5,428,492 →
Application: 07/930,737 →
Sine/Cosine Generator and Method
Patent: 5,276,633 →
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Semiconductor Rom Device and Method
Patent: 5,440,506 →
Application: 07/930,930 →
Method for Forming Recessed Oxide Isolation Containing Deep and Shallow Trenches
Patent: 5,382,541 →
Application: 07/935,765 →
Hermetic Package and Packaged Semiconductor Chip Having Closely Spaced Leads Extending Through the Package Lid
Patent: 5,209,390 →
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Circuit for Providing a Current Proportional to Absolute Temperature
Patent: 5,334,929 →
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Comparator Amplifier
Patent: 5,287,068 →
Application: 07/936,596 →
Stress Relief Technique of Removing Oxide from Surface of Trench- Patterned Semiconductor-on-Insulator Structure
Patent: 5,270,265 →
Application: 07/939,115 →
Bonded Wafer Processing with Metal Silicidation
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Inductive Load Dump Circuit
Patent: 5,347,169 →
Application: 07/941,736 →
Decimating Filter
Patent: 5,341,335 →
Application: 07/945,674 →
Reduction of Bipolar Gain and Improvement in Snap-Back Sustaining Voltage in Soi Field Effect Transistor
Patent: 5,315,144 →
Application: 07/947,177 →
Method for Forming Semiconductor Electrical Contacts Using Metal Foil and Thermocompression Bonding
Patent: 5,206,186 →
Application: 07/950,553 →
Non-Linear Operational Transconductance Amplifier
Patent: 5,307,023 →
Application: 07/962,309 →
Resource Access Security System for Controlling Access to Resources of a Data Processing System
Patent: 5,469,556 →
Application: 07/972,510 →
Integrated Heat Sink Having a Sinuous Fluid Channel for the Thermal Dissipation of Semiconductor Modules
Patent: 5,293,070 →
Application: 07/973,603 →
Device and Method for Improving Current Carrying Capability in a Semiconductor Device
Patent: 5,317,184 →
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Plural - Bit Recoding Multiplier
Patent: 5,262,976 →
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Amplifier System for Low Level Sensor Signal
Patent: 5,406,223 →
Application: 07/979,209 →
Amplifier with High Common Mode Rejection
Patent: 5,287,071 →
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Static Electricity Dispersant
Patent: 5,289,336 →
Application: 07/984,003 →
Electrostatic Discharge Protection
Patent: 5,416,351 →
Application: 07/984,187 →
Improved Sigma-Delta Type Analog-Digital Converter and Method
Patent: 5,345,236 →
Application: 07/993,585 →
Decoupling Tool Mechanism for Electrical Connectors
Patent: 5,312,262 →
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Spiral Edge Passivation Structure for Semiconductor Devices
Patent: 5,382,825 →
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Direct Thermocompression Bonding for Thin Electronic Power Chips
Patent: 5,304,847 →
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High Speed Differential Comparator
Patent: 5,329,187 →
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Circuit and Method for Extending the Safe Operating Area of a Bjt
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Bonded Wafer Process Incorporating Diamond Insulator
Patent: 5,272,104 →
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Curing of a Tungsten Filament in an Ion Implanter
Patent: 5,370,568 →
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Diamond Insulator Devices and Method of Fabrication
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Semi-Conductor Chip Packaging Method and Semi-Conductor Chip Having Interdigitated Gate Runners with Gate Bonding Pads
Patent: 5,366,932 →
Application: 08/051,832 →
Fast Turn on Switch Circuit with Parallel Mos Controlled Thyristor and Silicon Controlled Rectifier
Patent: 5,463,344 →
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Semicondcuctor Device with Increased Maximum Terminal Voltage Voltage
Patent: 6,008,512 →
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An Integrated Circuit with Improved Reverse Bias Breakdown
Patent: 5,373,183 →
Application: 08/053,244 →
Method of Making Intergrated Circuit Structure with Narrow Line Widths
Patent: 5,639,688 →
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Biasing of Island-Surrounding Material to Suppress Reduction of Breakdown Voltage Due to Field Plate Acting on Buried Layer/Island Junction Between High and Low Impurity Concentration Regions
Patent: 5,744,851 →
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Integrated Circuit Thermal Sensor
Patent: 5,359,236 →
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Voltage Divider and Use as Bias Network for Stacked Transistors
Patent: 5,493,207 →
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Process for Forming Twin Well Cmos Integrated Circuits
Patent: 5,429,958 →
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Differential Amplifier with Hysteresis
Patent: 5,367,211 →
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Trench Isolation Stress Relief
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Low Voltage Rf Amplifier and Mixer with Single Bias Block and Method
Patent: 5,809,410 →
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Fast Charging Mos Capacitor Structure for High Magnitude Voltage of Either Positive or Negative Polarity
Patent: 5,341,009 →
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Method and Device in Which Bottoming of a Well in a Dielectrically Isolated Island Is Assured
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Application: 08/091,819 →
Self-Aligned Channel Stop for Trench-Isolated Island
Patent: 5,436,189 →
Application: 08/106,160 →
Method for Interactively Tailoring Topography of Integrated Circuit Layout in Accordance with Electromigration Model-Based Minimum Width Metal and Contact/via Rules
Patent: 5,581,475 →
Application: 08/106,251 →
Semiconductor Device with a Foil Sealed Lid
Patent: 5,521,436 →
Application: 08/107,309 →
Sub-Micron Bonded Soi by Trench Planarization
Patent: 5,585,661 →
Application: 08/108,358 →
Fill and Etchback Process Using Dual Photoresist Sacrificial Layer and Two-Step Etching Process for Planarizing Oxide-Filled Shallow Trench Structure
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Methods for Forming a Transistor Having an Emitter with Enhanced Efficiency
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Die Separation Method for Silicon on Diamond Circuit Structures
Patent: 5,552,345 →
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High Frequency Analog Transistors, Method of Fabrication and Circuit Implementation
Patent: 5,668,397 →
Application: 08/131,369 →
Resistance-Measurement Based Arrangement for Monitoring Integrity of Travel Path Ground Link in Electronic Components Handling Apparatus
Patent: 5,576,695 →
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Method of Manufacture of Multi-Cell Integrated Circuit Architecture
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Wafer Bonding Using Trapped Oxidizing Vapor
Patent: 5,334,273 →
Application: 08/137,293 →
Comfet Switch and Method
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Mesh Geometry for Mos-Gated Semiconductor Devices
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Selective Recrystallization to Reduce P-Channel Transistor Leakage in Silicon-on-Sapphire Cmos Radiation Hardened Integrated Circuits
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Apparatus and Method for Increasing Breakdown Voltage Ruggedness in Semiconductor Devices
Patent: 5,424,563 →
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Package for Parallel Subelement Semiconductor Devices
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Fail-Safe Mos Shutdown Circuitry
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Voltage Independent Symmetrical Current Source with Cross-Coupled Transistors
Patent: 5,446,368 →
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Trench Resistor Architecture
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Method for Providing a Silicon and Diamond Substrate Having a Carbon to Silicon Transition Layer and Apparatus Thereof
Patent: 5,526,768 →
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Method of Making an Improved Graded Collector for Inductive Loads
Patent: 5,397,714 →
Application: 08/191,963 →
Differential Voltage Monitor Using a Bridge Circuit with Resistors on and Off an Integrated Circuit
Patent: 5,583,442 →
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Plasma Cleaning Method for Improved Ink Brand Permanency on Ic Packages with Metallic Parts
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Esd Protection Using Scr Clmaping
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Semiconductor Package and Method with Vertically Extended Electrode Leads
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Current Mirror with Saturation Limiting
Patent: 5,508,551 →
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Current Rise and Fall Time Limited Voltage Follower
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Application: 08/204,711 →
Reverse Current Flow Prevention in a Diffused Resistor
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Semiconductor Accelerometer and Method of Its Manufacture
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Hermetic Package for a High Power Semiconductor Device
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Application: 08/217,801 →
Device for Isolating Parallel Sub-Elements with Reverse Conducting Diode Regions
Patent: 5,594,261 →
Application: 08/223,425 →
Integration of High Voltage Lateral Mos Devices in Low Voltage Cmos Architecture Using Cmos-Compatible Process Steps
Patent: 5,541,435 →
Application: 08/227,157 →
Digital Baseband to If Conversion in Cellular Base Stations
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Application: 08/235,979 →
Method of Doping a Jfet Region in a Mos-Gated Semiconductor Device
Patent: 5,422,288 →
Application: 08/246,307 →
Silicon on Diamond Circuit Structure
Patent: 5,561,303 →
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High Voltage Protection Using Scrs
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Application: 08/253,287 →
Bridge Control Circuit and Method
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Process for Manufacturing a Multi-Port Adhesive Dispensing Tool
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Current Follower with Zero Input Impedance
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Impedance Setting Circuit for a Slic
Patent: 5,515,434 →
Application: 08/267,434 →
Ground Key Detector for a Slic
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Application: 08/267,436 →
Distortionless X-Ray Inspection
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Integrated Ringer Relay Circuit and Method
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High Speed a/D Converter and Slew Controlled Pulse Detector
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Graphical Display Discriminant Factor Indicator for Anomaly Identification in Semiconductor Manufacture Batch Process
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Semiconductor Device with Improved Turn-Off Capability
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Cmos Integrated Circuit Architecture Incorporating Deep Implanted Emitter Region to Form Auxiliary Bipolar Transistor
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Application: 08/276,290 →
Semi-Conductor Chip Having Interdigitated Gate Runners with Gate Bonding Pads
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Jfet Structures for Semiconductor Devices with Complementary Bipolar Transistors and Method of Making
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Method of Making Contact Regions for Narrow Trenches in Semiconductor Devices
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Analog-To-Digital Converter and Reference Voltage Circuitry
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Bonded Wafer Processing
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Trench Isolation Stress Relief
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High Speed Comparator
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Video Scaling Method and Device
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Half-Band Filter and Method
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Voltage Clamp Circuit and Method
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Wafer Bonding for Power Devices
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Method for Formation of a Well in a Dielectrically Isolated Island
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Fet, Igbt and Mct Structures to Enhance Operating Characteristics
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Programmable Element in Barrier Metal Device
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Structure and Tailoring Effective Resistivity of a Sipos Layer by Patterning and Control of Dopant Introduction
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Capacitor Structure in a Bonded Wafer and Method of Fabrication
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Sigma-Delta Analog to Digital Converter with Three Point Calibration Apparatus and Method
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Low Inductance Conductor Topography for Mosfet Circuit
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Bonded Wafer Processing
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Method for Making Ohmic Contact to Lightly Doped Islands from a Silicide Buried Layer and Applications
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Method for Forming Relessed Oxide Isolation Containing Deep and Shallow Trenches
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Differential Longitudinal Amplifier for a Subscriber Line Interface Circuit
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Multiport Memory and Method
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Multiport Memory and Method
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Bonded Wafer Processing with Metal Silicidation
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Methoe of Forming Mos-Gated Semiconductor Devices Having Mesh Geometry Pattern
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Switch Controller and Method
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Comfet Switch and Method
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Current Mode Ring Trip Detector
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Double Duty Capacitor Circuit and Method
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Circuit and Method for Loopback Test and on-Hook Transmission Integrated in a Telephone Subscriber Line Interface Circuit
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Filter with Reduced Element Ratings and Method
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Method and Circuit for Failsafe Switch-Hook Detection During Fault in a Telephone System
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Configuration Independent Auto-Biasing of Bipolar Transistor
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High Voltage, Junction Isolation Semiconductor Device Haivng Dual Conductivity Tape Buried Regions and Its Process of Manufacture
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Multiple Use Timer and Method for Pulse Width Generation, Echo Failure Detection, and Receive Pulse Width Measurement
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Surface Mountable Integrated Circuit with Conductive Vias
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Semiconductor Package and Method with Vertically Extended Electrode Leads
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Local Oxidation Process for High Field Threshold Applications
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High Efficiency Power Mos Switch
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Plasma Cleaning Method for Improved Ink Brand Permanency on Ic Packages
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Battery Operated Inverter Circuit for Capacitive Loads Such as Electroluminescent Lamps
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Electroluminescent Lamp Driver System
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Digital Decoder and Method for Decoding Composite Video Signals
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Automatic Fault Monitoring System and Motor Control System Incorporating Same
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Packet Header Generation and Detection Circuitry
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Testing Circuit and Method for a Codec Hybrid Balance Network
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Metal Oxide Semiconductor Controlled Thyristor with an on-Field Effect Transistor in a Trench
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Composition, and Method for Using Same, for Etching Metallic Alloys from a Substrate
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Method to Improve the Peak-Current Limit in a Slope-Compensated, Current-Mode Dc/Dc Converter, and Circuit Therefor
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Current-Controlled Carrier Tracking Filter for Improved Spurious Signal Suppression
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Phase Meter and Method of Providing a Voltage Indicative of a Phase Difference
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Circuit for Driving an Electroluminescent Lamp
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Asymmetric Snubber Resistor
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Carrier Buffer Having Current-Controlled Tracking Filter for Spurious Signal Suppression
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Analog-To-Digital Converter and Output Driver
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Integrated Circuit with an Air Bridge Having a Lid
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Double Diffused Mos Device and Method
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Integrated Circuit Containing Devices Dielectrically Isolated and Junction Isolated from a Substrate
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Silent Start Class D Amplifier
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Charge-Based Frequency Locked Loop and Method
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High Voltage Protection Circuits
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Negative Biasing of Isolation Trench Fill to Attract Mobile Positive Ions Away from Bipolar Device Regions
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Method of Making High Voltage, Junction Isolation Semiconductor Device Having Dual Conductivity Type Buried Regions
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Electrically Variable R/C Network and Method
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Lid Wafer Bond Packaging and Micromachining
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P-Collector H.V. Pmos Switch Vt Adjusted Source/Drain
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Two Trim Current Source and Method for a Digital-to-Analog Converter
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Method of Forming Power Semiconductor Devices with Controllable Integrated Buffer
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Low Distortion Feedback Ic Amplifier and Method
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Digital- to- Analog Converter Having Enhanced Current Steering and Associated Method
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Wide Common Mode Range Comparator and Method
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Switching Amplifier Closed Loop Dual Comparator Modulation Technique
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Gain Control Circuit and Method
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Integrated Circuit Having Enhanced Transient Voltage Protection and Associated Methods
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Surface Mount Die by Handle Replacement
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Reconfigurable Filter System
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Analog-To-Digital Converter and Method of Fabrication
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Capacitor Structure in a Bonded Wafer and Method of Fabrication
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Late Process Method and Apparatus for Trench Isolation
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Driver Circuit Providing Controllable Battery Overload Protection
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Method for Cleaning Semiconductor Wafers to Improve Dice to Substrate Solderability
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Plsma Cleaning Method for Improved Ink Brand Permanency on Ic Packages
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Method of Metalizing a Semiconductor Power Device Ceramic Member
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Deep Trench Etch on Bonded Silicon Wafer
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Process for Doping Two Levels of a Double Poly Bipolar Transistor After Formation of Second Poly Layer
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Process for Doping Two Levels of a Double Poly Bipolar Transistor After Formation of Second Poly Layer
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Complementary Mutliplexer with Low Disabled-Output Capacitance, and Method
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Re-Sampling Circuit and Modulator Using Same
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Interpolator Using a Plurality of Polynomial Equations and Associated Methods
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High Frequency Analog Transistors, Method of Fabrication and Circuit Implementation
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Pivot Sample Block Cross-Section Tool
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Integrated Circuit with Thin Film Resistors and a Method for Co-Patterning Thin Film Resistors with Different Compositions
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Dc-To-Dc Converter Having Enhanced Control Features and Associated Methods
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Dc-To-Dc Converter Having Fast Over-Current Detection and Associated Methods
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Dc-To-Dc Converter Having Charge Pump and Associated Methods
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Ohmic Contact to Lightly Doped Islands from a Conductive Rapid Diffusion Buried Layer
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Method of Making Mos-Gated Semiconductor Devices
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High Data Rate Spread Spectrum Transceiver and Associated Methods
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Contact Regions for Narrow Trenches in Semiconductor Devices and Method
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Circuit and Method for Synchronizing Outputs of Two Simultaneously Transmitting Devices in a Multiplexed Communication System
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Reduce Width, Differentially Doped Vertical Jfet Device
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Integrated Circuit Chip Structure for Improved Packaging
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One Mask, Power Semiconductor Device Fabrication Process
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Level Shifter Stage with Punch Through Diode
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Punch-Through Diodes and Applications
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Single Ended to Differential Converter and 50% Duty Cycle Signal Generator and Method
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Temperature Insensitive Bandgap Voltage Generator Tracking Power Supply Variations
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Dynamic Regulator for a Dc-to-Dc Power Converter and Related Methods
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Non-Uniformly Nitrided Gate Oxide and Method
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Low Voltage Rf Amplifier and Mixed with Single Bias Block and Method
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Self-Aligned Power Field Effect Transistor in Silicon Carbide
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Silicon-Glass Bonded Wafers
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Bipolar Semiconductor Power Controlling Devices with Heterojunction
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Method and Apparatus for Calibrating Integrated Circuit Analog-to-Digital Converters
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Processor Controlled Analog-to-Digital Converter Circuit
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Method for Forming Complementary Wells and Self-Aligned Trench with a Single Mask
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Method of Making a Mos-Gated Semiconductor Device with a Single Diffusion
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Lifetime Control for Semiconductor Devices
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Trench Contact Process
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Multilayer Microtip Probe and Method
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A Method of Fabricating Umos Semiconductor Devices Using a Self-Aligned, Reduced Mask Process
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Semiconductor Structures with Trench Contacts
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Hermetic Thin Oack Semiconductor Device
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Bonded Wafer Processing with Metal Silicidation
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Digital-To-Analog Converter Including Current Cell Matrix with Enhanced Linearity and Associated Methods
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Electrical System with Small Signal Suppression Circuitry
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Comparator with Small Signal Suppression Circuitry
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Constant Slew Rate Amplifier
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Knock Sensor System for Detecting and Responding to a Disconnect Condition
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Frequency Dependent Resistive Element
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Protection Device for Solid State Switched Power Electornics
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Method Fo Fabricating Bicmos Devices
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Inverted Thin Film Resistor
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Schmitt Trigger-Configured Esd Protection Circuit
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High Voltage Mosfet Structure
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Negative Biasing of Isolation Trench Fill to Attract Mobile Positive Ions Away from Bipolar Device Regions
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Low Distortion Current Feedback Amplifier with Dynamic Biasing
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Monolithic Class D Amplifier
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Multiple Output Dc-to-Dc Converter Having Enhanced Noise Margin and Related Methods
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Power Mosfet with an Anode Region
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Rf Communications System Operable in the Presence of a Repetitive Interference Source and Related Methods
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Class D Amplifier with Scaled Clock and Related Methods
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Adjustable Phase Clock Circuit Using Same and Related Methods
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Class D Amplifier with Reduced Clock Requirement and Related Methods
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Optimum Placement of Bypass Capacitors in a Network for Improving Electro-Magnetic Interference Response
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Trench Emitter Controlled Thyristor
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Network for Improving Electro-Magnetice Interference Response
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Ring Generator
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Igbt Gate Drive Circuit with Short Circuit Protection
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Devices Formable by Low Temperature Direct Bonding
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Methods for Making Semiconductor Devices by Low Temperature Direct Bonding
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Sample-And-Hold Circuit Having Reduced Subthreshold Conduction Effects and Related Methods
Patent: 6,069,502 →
Application: 09/055,528 →
Sample-And-Hold Circuit Having Reduced Parasitic Diode Effects and Related Methods
Patent: 6,002,277 →
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Sample-And-Hold Circuit Having Reduced Amplifier Offset Effects and Related Methods
Patent: 6,016,067 →
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Vacuum Processing Apparatus and Operating Method Therefor
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Devices with Patterned Wells and Method for Forming Same
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Publication: US 2002/0158312
Sc-2 Based Pre-Thermal Treatment Wafer Cleaning Process
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Lid Wafer Bond Packaging and Micromachining
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Battery Switching Subscriber Loop Interface Circuit
Patent: 6,233,335 →
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Defect Gettering by Induced Stress
Patent: 5,929,508 →
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Circuit and Method for Protecting from Overcurrent Conditions and Detecting an Open Electrical Load
Patent: 5,920,452 →
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Methods of Forming Power Semiconductor Devices Having Merged Split-Well Body Regions Therein
Patent: 6,121,089 →
Application: 09/092,334 →
Trench Mos Gate Device
Patent: 6,368,920 →
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High Performance Heat Exchanger and Method
Patent: 6,196,307 →
Application: 09/098,517 →
Decapsulating Method and Apparatus for Integrated Circuit Packages
Patent: 6,054,012 →
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Heat Exchanging Chassis
Patent: 6,188,575 →
Application: 09/107,273 →
Method of Creating a Solderable Metal Layer on Glass or Ceramic
Patent: 6,159,663 →
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Semiconductor Device Having Reduced Effective Substrate Resistivity and Associatd Methods
Patent: 6,104,062 →
Application: 09/107,721 →
Linear Voltage Regulator Compatible with Bipolar and Mosfet Pass Devices and Associated Methods
Patent: 6,005,303 →
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High Voltage Semiconductor Structure
Patent: 6,066,878 →
Application: 09/108,962 →
Electrostatic Discharge Locating Apparatus and Method
Patent: 6,064,340 →
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Flat Power Rack
Patent: 6,057,612 →
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Surface Mount Die by Handle Replacement
Patent: 6,114,768 →
Application: 09/110,721 →
Parasitic Current Barriers
Patent: 6,278,186 →
Application: 09/139,932 →
Programmable Subscriber Loop Interface Circuit and Method
Patent: 6,665,398 →
Application: 09/145,182 →
Method of Making Shallow Well Mosfet Structure
Patent: 6,107,127 →
Application: 09/145,513 →
Analog-To-Digital Converter Having Enhanced Accuracy Gain Stage, and Associated Devices and Methods
Patent: 6,107,950 →
Application: 09/148,955 →
Digital-To-Analog Converter Including Current Sources Operable in a Predetermined Sequence and Associated Methods
Patent: 6,118,398 →
Application: 09/149,154 →
Device Containing Sample Preparation Sites for Transmission Electron Microscopic Analysis and Processes of Formation and Use
Patent: 6,140,652 →
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Driver Circuit Having Load-Independent Slew Rate
Patent: 6,172,541 →
Application: 09/152,420 →
Pulsed Beacon-Based Interference Reduction Mechanism for Wireless Communication Networks
Patent: 6,377,608 →
Application: 09/163,802 →
Semiconductor Integrated Circuit with Temporarily Interconnected Bond Pads
Application: 09/166,416 →
Process for Forming High Voltage Junction Termination Extension Oxide
Patent: 6,309,952 →
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Publication: US 2001/0041461
Power Module with Lowered Inductance and Reduced Voltage Overshoots
Patent: 6,069,403 →
Application: 09/167,203 →
Variable Frequency Class D Modulator with Built in Soft Clipping and Frequency Limiting
Patent: 6,107,875 →
Application: 09/173,111 →
Overcurrent Sensing Circuit and Self Adjusting Blanking.
Patent: 6,108,182 →
Application: 09/183,453 →
Start-Up Circuit for Self Oscillating Class D Modulator
Patent: 6,118,336 →
Application: 09/183,879 →
Integrated Circuit Air Bridge Structures and Methods of Fabricating Same
Patent: 6,211,056 →
Application: 09/199,292 →
Current Limited, Thermally Protected, Power Device
Patent: 6,055,149 →
Application: 09/203,700 →
Semiconductor Packaging Method
Patent: 6,114,191 →
Application: 09/204,904 →
Apparatus and Method for Testing Subscriber Loop Interface Circuits
Patent: 6,519,322 →
Application: 09/208,457 →
Dc-To-Dc Converter with Inductor Current Sensing and Related Methods
Patent: 5,982,160 →
Application: 09/220,780 →
Wireless Local Area Network Spread Spectrum Transceiver with Multipath Mitigation
Patent: 6,678,310 →
Application: 09/231,184 →
Spread Spectrum Transceiver for Use in Wireless Local Area Network and Having Multipath Mitigation
Patent: 6,603,801 →
Application: 09/231,228 →
Method of Performing Antenna Diversity in Spread Spectrum in Wireless Local Area Network
Patent: 6,563,858 →
Application: 09/231,608 →
Frequency Dependent Resistive Element
Patent: 5,999,080 →
Application: 09/246,815 →
Complementary Multiplexer with Low Disabled-Output Capacitance, and Method
Patent: 6,114,896 →
Application: 09/247,510 →
Method for Forming a Bonded Substrate Containing a Planar Intrinsic Gettering Zone and Substrate Formed by Said Method
Patent: 6,255,195 →
Application: 09/255,231 →
Mos-Gated Device Having a Buried Gate and Process for Forming Same
Patent: 6,351,009 →
Application: 09/260,411 →
Feedback-Controlled Low Voltage Current Sink/Source
Patent: 6,172,556 →
Application: 09/261,981 →
Integrated Circuit with Deep Trench Having Multiple Slopes
Patent: 6,198,150 →
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Method for Fabricating Electrostatic Discharge Protection Device
Patent: 6,051,457 →
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Wafer Trench Article and Process
Patent: 6,365,953 →
Application: 09/283,530 →
Publication: US 2001/0045614
High Density Mos-Gated Power Device and Process for Forming Same
Patent: 6,188,105 →
Application: 09/283,531 →
Power Trench Mos-Gated Device and Process for Forming Same
Application: 09/283,536 →
Publication: US 2001/0001494
Power Mos Device with Increased Channel Width and Process for Forming Same
Patent: 6,218,701 →
Application: 09/303,270 →
Process for Forming Mos-Gated Devices Having Self-Aligned Trenches
Patent: 6,238,981 →
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Laser Decapsulation Method
Patent: 6,335,208 →
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Mos-Gated Power Device Having Extended Trench and Doping Zone and Process for Forming Same
Patent: 6,198,127 →
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Bonded Wafer with Metal Silicidation
Patent: 6,909,146 →
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Trench-Gated Device Having Trench Walls Formed by Selective Epitaxial Growth and Process for Forming Device
Patent: 6,373,098 →
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Low Voltage Dual-Well Mos Device Having High Ruggedness, Low on-Resistance, and Improved Body Diode Reverse Recovery
Patent: 6,137,139 →
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Power Device
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Power Module with Lowered Inductance and Reduced Voltage Overshoots
Patent: 6,140,152 →
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Self-Supported Ultrathin Silicon Wafer Process
Patent: 6,162,702 →
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Defect Gettering by Induced Stress
Patent: 6,274,460 →
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Current-Controlled Carrier Tracking Filter for Improved Spuriou Signal Suppression
Patent: 6,233,293 →
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Sc-2 Based Pre-Thermal Treatment Wafer Cleaning Process
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Publication: US 2002/0189640
Semiconductor Device Gate Structure for Thermal Overload Protection
Patent: 6,236,088 →
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Method of Forming an Integrated Resistive Contacts with Mobility Spoiling Ions Including High Resistivity Contacts and Low Resistivity Silicide Contacts
Patent: 6,403,472 →
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Backmetal Drain Terminal with Low Stress and Thermal Resistance
Patent: 6,211,550 →
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Dual Mode Class D Amplifiers
Patent: 6,587,670 →
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Rake Receiver with Embedded Decision Feedback Equalizer
Patent: 6,233,273 →
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Brushless Multipass Silicon Wafer Cleaning Process for Post Chemical Mechanical Polishing Using Immersion
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Method of Manufacturing a Plated Electronic Termination
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Potted Transducer Array with Matching Network in a Multiple Pass Configuration
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Method for Making a Diffused Back-Side Layer on a Bonded-Wafer with a Thick Bond Oxide
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Low Temperature Coefficient Resistor (Tcrl)
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Power Semiconductor Mounting Package Containing Ball Grid Array
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Process for Forming Vertical Semiconductor Device Having Increased Source Contact Area
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Class D Modulator with Digital Current Limit and Load Impedance Sensing Circuits
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Class D Amplifier with Very Low Jitter Dead Time
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Class D Amplifier with Bandwidth Independent of Load Impedance
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Apparatus and Method for Minimizing Currents in Discrete Electrical Devices
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Accessing Main Atx Outputs Without Monitoring All Outputs
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Related Assignments (10)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. Dec 7, 1981
From: STEWART, ROGER G.
To: RCA CORPORATION
Reel/Frame 003964/0393 →
Assignment of Assignors Interest. Apr 28, 1982
From: SHACKLE, PETER W.; POSPISIL, ROBERT S.
To: HARRIS CORPORATION, A CORP. OF DEL.
Reel/Frame 003997/0217 →
Assignment of Assignors Interest. Jan 21, 1983
From: PRABHU, ASHOK N.; HANG, KENNETH W.
To: RCA CORPORATION, A CORP. OF DE
Reel/Frame 004087/0111 →
Assignment of Assignor's Interest Sep 11, 1999
From: HARRIS CORPORATION
To: INTERSIL CORPORATION
Reel/Frame 010255/0405 →
Assignment of Assignor's Interest Sep 27, 1999
From: HARRIS CORPORATION
To: INTERSIL CORPORATION
Reel/Frame 010247/0043 →
Assignment of Assignor's Interest Sep 28, 1999
From: HARRIS SEMICONDUCTOR PATENTS, INC.
To: INTERSIL CORPORATION
Reel/Frame 010247/0161 →
Intellectual Property Partial Release Mar 16, 2001
From: CREIDT SUISSE FIRST BOSTON
To: INTERSIL HOLDING CORPORATION
Reel/Frame 011667/0166 →
Reassignment of Patent Applications Jul 16, 2001
From: INTERSIL CORPORATION
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 012002/0206 →
Security Agreement May 5, 2010
From: INTERSIL CORPORATION; TECHWELL, INC.; INTERSIL COMMUNICATIONS, INC.; QUELLAN, INC.
To: MORGAN STANLEY & CO. INCORPORATED
Reel/Frame 024390/0608 →
Release of Security Interest May 26, 2010
From: CREDIT SUISSE FIRST BOSTON
To: INTERSIL CORPORATION
Reel/Frame 024445/0049 →