IP Library › Assignment 010247/0161
Patent Assignment
Reel/Frame 010247/0161

Assignment of Assignor's Interest

Recorded: 1999-09-28 Pages: 13
Assignor
HARRIS SEMICONDUCTOR PATENTS, INC.
Executed: 1999-08-13
Assignee
INTERSIL CORPORATION
2401 PALM BAY ROAD, N.E., PALM BAY, FLORIDA, 32905
Covered Properties (414)
Ballasted Gate Controlled Semiconductor Device
Patent: 4,561,008 →
Application: 05/870,484 →
Five Transistor Cmos Memory Cell Including Diodes
Patent: 4,724,530 →
Application: 05/948,103 →
Vertical Mosfet with Reduced Turn-on Resistance
Patent: 4,366,495 →
Application: 06/063,809 →
Silicon Mos Inductor
Patent: 4,282,537 →
Application: 06/068,013 →
Mnos Memory Device and Method of Manufacture
Patent: 4,305,086 →
Application: 06/070,020 →
Blocked Source Node Field-Effect Circuitry
Patent: 4,253,162 →
Application: 06/070,509 →
Differential-Input Amplifier Circuit
Patent: 4,272,728 →
Application: 06/070,510 →
Starting Circuit for Low Power Oscillator Circuit
Patent: 4,282,496 →
Application: 06/070,703 →
Free Hold Down of Wafers for Material Removal
Patent: 4,258,508 →
Application: 06/072,430 →
Measurement of a Gas Constituent by a Mass Spectrometer
Patent: 4,260,886 →
Application: 06/073,199 →
Method of Defining a Photoresist Layer
Patent: 4,239,790 →
Application: 06/075,162 →
Positive Resist for Electron Beam and X-Ray Lithography and Method of Using Same
Patent: 4,262,083 →
Application: 06/076,673 →
Operational Transconductance Amplifiers with Non-Linear Component Current Amplifiers
Patent: 4,267,519 →
Application: 06/076,674 →
Relative Humidity Measurement
Patent: 4,227,411 →
Application: 06/077,913 →
Fabrication of an Integrated Injection Logic Device with Narrow Base Width
Patent: 4,244,001 →
Application: 06/080,101 →
Look Ahead High Speed Circuitry
Patent: 4,242,738 →
Application: 06/081,040 →
Amplifier Circuit Having Controllable Gain
Patent: 4,305,044 →
Application: 06/081,087 →
Temperature Gradient Means in Reactor Tube of Vapor Deposition Apparatus
Patent: 4,256,052 →
Application: 06/081,193 →
Chuck for Use in Testing of Semiconductor Pellets
Patent: 4,327,325 →
Application: 06/081,194 →
Method of Making an Impatt Diode
Patent: 4,230,505 →
Application: 06/082,733 →
Method of Detecting a Thin Insulating Film Over a Conductor
Patent: 4,296,370 →
Application: 06/083,640 →
Overload Protection Circuit for Output Driver
Patent: 4,329,600 →
Application: 06/084,711 →
Two Input Sense Circuit
Patent: 4,321,492 →
Application: 06/084,712 →
Gate Injected Floating Gate Memory Device
Patent: 4,253,106 →
Application: 06/086,313 →
Multi-Mode Oscillator
Patent: 4,250,500 →
Application: 06/087,447 →
Means to Orbit and Rotate Target Wafers Supported on Planet Member
Patent: 4,284,033 →
Application: 06/089,858 →
Partially Devitrified Porcelain Composition and Articles Prepared with Same
Patent: 4,256,796 →
Application: 06/091,091 →
Low Leakage N-Channel Sos Transistors and Method of Making Them
Patent: 4,252,574 →
Application: 06/093,011 →
Method of Detecting a Cathodic Corrosion Site on a Metallized Substrate
Patent: 4,278,508 →
Application: 06/093,214 →
Method of Manufacturing Submicron Channel Transistors
Patent: 4,313,782 →
Application: 06/094,215 →
Amplifier with Cross-Over Current Control
Patent: 4,297,644 →
Application: 06/096,739 →
Positive Resist Medium and Method of Employing Same
Patent: 4,262,073 →
Application: 06/096,973 →
Class Ab Push-Pull Amplifiers
Patent: 4,335,360 →
Application: 06/097,040 →
Method for Manufacturing a Self-Aligned Contact in a Grooved Semiconductor Surface
Patent: 4,268,537 →
Application: 06/099,598 →
Push-Push Resonant Power Inverter
Patent: 4,250,541 →
Application: 06/101,165 →
Optically Testing the Lateral Dimensions of a Pattern
Patent: 4,303,341 →
Application: 06/101,166 →
Reference Current Supply Circuits
Patent: 4,282,478 →
Application: 06/101,848 →
Class Ab Push-Pull Quasi-Linear Amplifiers
Patent: 4,295,101 →
Application: 06/102,131 →
Circuit with Dual-Purpose Terminal
Patent: 4,350,906 →
Application: 06/102,574 →
Low Power Switch Closure Sensing Circuit
Patent: 4,303,907 →
Application: 06/103,924 →
Compensation for Transistor Output Resistance
Patent: 4,311,967 →
Application: 06/104,372 →
Battery Test System, as for Smoke Detector Alarm
Patent: 4,251,811 →
Application: 06/106,656 →
Small Signal Memory System with Reference Signal
Patent: 4,270,190 →
Application: 06/106,882 →
Signal Comparison Circuit
Patent: 4,348,596 →
Application: 06/107,403 →
Circuit for Reducing the Loading Effect of an Insulated-Gate Field-Effect Transistor (Igfet) on a Signal Source
Patent: 4,281,400 →
Application: 06/108,222 →
Method for Forming Buried Contact Complementary Mos Devices
Patent: 4,276,688 →
Application: 06/113,505 →
Extended Drain Self-Aligned Silicon Gate Mosfet
Patent: 4,318,216 →
Application: 06/116,789 →
Method of Manufacturing Short Channel Mos Devices
Patent: 4,263,057 →
Application: 06/116,896 →
Radiation Heated Reactor for Chemical Vapor Deposition on Substrates
Patent: 4,263,872 →
Application: 06/117,236 →
Use of Silicide to Bridge Unwanted Polycrystalline Silicon P-N Junction
Patent: 4,333,099 →
Application: 06/118,089 →
Series Voltage Regulators for Developing Temperature-Compensated Voltages
Patent: 4,282,477 →
Application: 06/120,471 →
Fast Level Shift Circuits
Patent: 4,314,166 →
Application: 06/123,714 →
Position Sensing and Display Means
Patent: 4,294,321 →
Application: 06/125,118 →
Method of Applying Thin Metal Deposits to a Substrate
Patent: 4,297,393 →
Application: 06/125,639 →
Differential-Input Amplifier Circuitry with Increased Common-Mode Voltage Range
Patent: 4,345,213 →
Application: 06/125,645 →
Current Dividers Using Emitter-Coupled Transistor Pairs
Patent: 4,284,945 →
Application: 06/128,872 →
Method of Improving Silicon Crystal Perfection in Silicon on Sapphire Devices
Patent: 4,279,688 →
Application: 06/131,046 →
Amplifier Using Lateral and Vertical Transistors
Patent: 4,334,196 →
Application: 06/131,518 →
Cmos Device with Silicided Sources and Drains and Method
Patent: 4,336,550 →
Application: 06/132,138 →
Centering Support for a Rotatable Wafer Support Susceptor
Patent: 4,275,282 →
Application: 06/132,878 →
Method for Measuring the Drift Mobility in Doped Semiconductors
Patent: 4,319,187 →
Application: 06/133,253 →
Differential-Input Complementary Field-Effect Transistor Amplifier
Patent: 4,333,057 →
Application: 06/133,254 →
A Method for the Manufacture of Boards Having Interconnections Between the Top and Bottom Surfaces
Patent: 4,328,614 →
Application: 06/133,255 →
Power Mosfet with an Anode Region
Patent: 4,364,073 →
Application: 06/133,902 →
Method of Manufacturing Submicron Channel Transistors
Patent: 4,312,680 →
Application: 06/136,157 →
Three-Condition Display System
Patent: 4,321,543 →
Application: 06/139,714 →
Precharge Circuit
Patent: 4,352,031 →
Application: 06/143,025 →
Circuitry for Generating Electric Signals with Proportional, Opposite- Sense Rates of Change
Patent: 4,322,691 →
Application: 06/143,346 →
Biasing of Transistor Amplifier Cascades
Patent: 4,334,198 →
Application: 06/143,504 →
Operational Amplifier Employing Complementary Field-Effect Transistors
Patent: 4,333,058 →
Application: 06/144,291 →
Random Access Memory with Volatile and Non-Volatile Storage
Patent: 4,354,255 →
Application: 06/144,922 →
Memory Circuit with Means for Compensating for Inversion of Stored Data
Patent: 4,337,522 →
Application: 06/145,324 →
Method of Treating Sipos Passivated High Voltage Semiconductor Device
Patent: 4,297,149 →
Application: 06/146,380 →
Method of Laying Out an Integrated Circuit with Specific Alignment of the Collector Contact with the Emitter Region
Patent: 4,272,882 →
Application: 06/147,574 →
Transistor Amplifiers Exhibiting Low Input Offset Potentials
Patent: 4,360,785 →
Application: 06/153,627 →
Reference Poential Generating Circuits
Patent: 4,302,718 →
Application: 06/153,628 →
Plural Output Switched Current Amplifier as for Driving Light Emitting Diodes
Patent: 4,417,240 →
Application: 06/153,629 →
Amplifier Circuits
Patent: 31,263 →
Application: 06/153,630 →
Wafer and Boule Protection During the Blade Return Stroke of a Wafer Saw
Patent: 4,326,494 →
Application: 06/153,632 →
Method and Apparatus for Determining Minority Carrier Diffusion Length in Semiconductors
Patent: 4,333,051 →
Application: 06/153,920 →
Method for Determining Silicon Content in Layers of Aluminum and Silicon
Patent: 4,282,266 →
Application: 06/154,598 →
Low Leakage N-Channel Sos Transistors and Method of Making Them
Patent: 4,393,572 →
Application: 06/154,601 →
Wafer and Boule Protection During the Blade Return Stroke of a Wafer Saw
Patent: 4,287,256 →
Application: 06/155,999 →
Etching Tank in Which the Solution Circulates by Convection
Patent: 4,302,273 →
Application: 06/156,889 →
Semiconductor Power Device Having Second Breakdown Protection
Patent: 4,291,324 →
Application: 06/161,453 →
Digital Timing System for Spark Advance
Patent: 4,375,209 →
Application: 06/161,454 →
Wettable Carrewe in Gas Drying System for Wafers
Patent: 4,318,749 →
Application: 06/162,086 →
Compensation of Base-Current-Related Error in Current Mirror Amplifier Circuitry
Patent: 4,345,216 →
Application: 06/162,939 →
Plasma Etching Device and Process
Patent: 4,304,983 →
Application: 06/163,148 →
Electron Flood Exposure Apparatus
Patent: 4,321,470 →
Application: 06/164,069 →
Current Mirror Amplifiers with Programmable Gain
Patent: 4,361,816 →
Application: 06/164,139 →
Self Aligned Aluminum Polycrystalline Silicon Contact
Patent: 4,380,773 →
Application: 06/164,345 →
Power Protection Circuit for Transistors
Patent: 4,355,341 →
Application: 06/164,347 →
Electrically Programmable Logic Array
Patent: 4,313,106 →
Application: 06/164,677 →
Method of Manufacturing Bulk Cmos Integrated Circuits
Patent: 4,295,266 →
Application: 06/164,681 →
Operational Amplifier with Programmable Gain
Patent: 4,361,815 →
Application: 06/164,682 →
Multi-Mode Circuit
Patent: 4,317,110 →
Application: 06/164,683 →
Rf Heating Coil Construction for Stack of Susceptors
Patent: 4,339,645 →
Application: 06/165,740 →
Semiconductor Power Device Incorporating a Schottky Barrier Diode Between Base and Emitter of a Pnp Device
Patent: 4,253,105 →
Application: 06/165,760 →
High-Current, High-Voltage Semiconductor Devices Having a Metallurgical Grade Substrate
Patent: 4,383,268 →
Application: 06/166,347 →
Current Regulating Circuitry
Patent: 4,300,091 →
Application: 06/167,696 →
Method of Making Semiconductor Device with Passivated Rectifying Junctions Having Hydrogenated Amorphous Regions
Patent: 4,315,782 →
Application: 06/170,813 →
Method for End Ppint Detection in a Plasma Etching Process
Patent: 4,328,068 →
Application: 06/171,271 →
Dual Output Switching Circuit
Patent: 4,337,423 →
Application: 06/171,833 →
Method for Fabricating Adjacent Conducting and Insulating Regions in a Film by Laser Irradiation
Patent: 4,339,285 →
Application: 06/172,757 →
Apparatus and Method for Neutralizing the Beam in an Ion Implanter
Patent: 4,361,762 →
Application: 06/173,630 →
Pulse Counter Type Circuit for Power-Up Indication
Patent: 4,365,174 →
Application: 06/174,184 →
Method for Forming an Improved Gate Member Utilizing Special Masking and Oxidation to Eliminate Projecting Points on Silicon Islands
Patent: 4,277,884 →
Application: 06/174,845 →
Method of Forming an Improved Gate Member for a Gate Injected Floating Gate Memory Device
Patent: 4,334,347 →
Application: 06/175,757 →
Temperature-Correction Network for Extrapolated Band-Gap Voltage Reference Circuit
Patent: 4,325,017 →
Application: 06/177,913 →
Bow-Correction Network with Multiple Corrections for Extrapolated Band -Gap Voltage Reference Circuit
Patent: 4,325,018 →
Application: 06/177,915 →
Duty Cycle Generator with Improved Resolution
Patent: 4,365,202 →
Application: 06/180,903 →
Susceptor for Heating Semiconductor Substrates
Patent: 4,322,592 →
Application: 06/181,376 →
Digital Timing System for Spark Advance
Patent: 4,408,296 →
Application: 06/181,941 →
Megasonic Jet Cleaner Apparatus
Patent: 4,326,553 →
Application: 06/181,985 →
Thin Film Thickness Monitor
Patent: 4,355,903 →
Application: 06/181,990 →
Field Effect Transistor Amplifier with Variable Gain Control
Patent: 4,353,036 →
Application: 06/182,787 →
Switch Closure Sensing Circuit
Patent: 4,318,087 →
Application: 06/184,952 →
Noise Protection Circuits
Patent: 4,339,809 →
Application: 06/188,887 →
Method and Apparatus for Determining the Quality of a Semiconductor Surface
Patent: 4,352,016 →
Application: 06/189,348 →
Apparatus for Determining the Quality of a Semiconductor Surface
Patent: 4,352,017 →
Application: 06/189,356 →
Bridge Amplifiers Employing Complementary Field-Effect Transistors
Patent: 4,355,287 →
Application: 06/192,363 →
Gated Oscillator Including Initialization Apparatus for Enhancing Periodicity
Patent: 4,365,212 →
Application: 06/192,364 →
Borosilicate Glass Frit with Mgo and Bao
Patent: 4,355,115 →
Application: 06/193,712 →
Method of Reducing Edge Current Leakage in N Channel Silicon-on-Sapphire Devices
Patent: 4,313,809 →
Application: 06/197,286 →
Method of and Apparatus for Outgassing Raw Material Used to Grow Crystals
Patent: 4,305,725 →
Application: 06/198,833 →
Quantizing Circuits Using a Charge Coupled Device with a Feedback Channel
Patent: 4,369,378 →
Application: 06/201,191 →
Radiation Heated Reactor Process for Chemical Vapor Deposition on Substrates
Patent: 4,401,689 →
Application: 06/201,437 →
Laminated Conducting Film on an Integrated Circuit Substrate and Method of Forming the Laminate
Patent: 4,302,498 →
Application: 06/201,438 →
Method of Forming a Mesa in a Semiconductor Device with Subsequent Separation into Individual Devices
Patent: 4,355,457 →
Application: 06/201,826 →
Current Amplifier
Patent: 4,380,740 →
Application: 06/202,485 →
Photocurrent Compensation for Electronic Circuitry Exposed to Ionizing Radiation
Patent: 4,380,741 →
Application: 06/205,341 →
Testing Semiconductor Furnaces for Heavy Metal Contamination
Patent: 4,420,722 →
Application: 06/206,715 →
Positive Resist for Electron Beam and X-Ray Lithography and Method of Using Same
Patent: 4,330,671 →
Application: 06/206,716 →
Power Transformer with High Coupling Coefficient
Patent: 4,320,373 →
Application: 06/207,720 →
Monitor for Oxygen Concentration in Aluminum-Based Films
Patent: 4,348,886 →
Application: 06/208,704 →
New Water-Based Photoresists Using Stilbene Compounds as Crosslinking Agents
Patent: 4,299,910 →
Application: 06/209,535 →
Self-Quenching Circuit
Patent: 4,382,192 →
Application: 06/211,342 →
Vehicle Multiplex System
Patent: 4,370,561 →
Application: 06/211,343 →
Circuit and Method for Duty Cycle Control
Patent: 4,355,283 →
Application: 06/211,349 →
Transistor with Improved Second Breakdown Capability
Patent: 4,388,634 →
Application: 06/212,813 →
Retainer Ring for Securing Substrates in a Vacuum Deposition System
Patent: 4,344,383 →
Application: 06/215,004 →
Xenon Flash Lamp Shield
Patent: 4,378,583 →
Application: 06/215,089 →
Aqueous Developable Poly (Olefin Sulfone) Terpolymers
Patent: 4,341,861 →
Application: 06/219,517 →
Semiconductor Device Passivated with Phosilicate Glass Over Silicon Nitride
Patent: 4,668,973 →
Application: 06/221,367 →
Temperature-Independent Current Trimming Arrangement
Patent: 4,366,444 →
Application: 06/230,382 →
Protective Integrated Circuit Device Utilizing Back-to-Back Zener Diodes
Patent: 4,405,933 →
Application: 06/231,288 →
Precharge with Power Conservation
Patent: 4,405,996 →
Application: 06/232,303 →
Pulse Generating Circuit Using Current Source
Patent: 4,386,284 →
Application: 06/232,360 →
Transistor with Integrated Diode and Resistor
Patent: 4,398,206 →
Application: 06/233,488 →
Vertical Mosfet with an Aligned Gate Electrode and Aligned Drain Shield Electrode
Patent: 4,455,565 →
Application: 06/234,834 →
Method for Improving Adhesion of Metal Film on a Dielectric Surface
Patent: 4,404,235 →
Application: 06/237,415 →
Over-Current Protection Circuits for Power Transistors
Patent: 4,321,648 →
Application: 06/237,872 →
Crystal Seed Holder Assembly
Patent: 4,348,365 →
Application: 06/242,046 →
Partially Devitrified Porcelain Containing Bao. 2MGO.2SIO2.,and 2MGO. B2O3 Crystalline Phases Obtained from Alkali Metal Free Divalent Metal Oxide Borosilicate Glass
Patent: 4,355,114 →
Application: 06/242,418 →
Silicon Melting Crucible
Patent: 4,356,152 →
Application: 06/243,441 →
Positive Radiation Sensitive Resist Terpolymers
Patent: 4,355,094 →
Application: 06/244,104 →
Method for Forming a Narrow Thin Film Line
Patent: 4,324,814 →
Application: 06/245,589 →
Operational Amplifier Employing Complementary Field-Effect Transistors
Patent: 4,377,789 →
Application: 06/246,027 →
Method of Depositing a Refractory Metal on a Semiconductor Substrate
Patent: 4,349,408 →
Application: 06/248,038 →
Method of Passivating a Semiconductor Device with a Multi-Layer Passivant System by Thermally Growing a Layer of Oxide on an Oxygen Doped Polycrystalline Silicon Layer
Patent: 4,344,985 →
Application: 06/248,208 →
Integrated Circuit Protection Device
Patent: 4,400,711 →
Application: 06/249,612 →
Operational Amplifier with Feed-Forward Compensation Circuit
Patent: 4,410,857 →
Application: 06/258,406 →
Radiation Shadow Projection Exposure System
Patent: 4,348,105 →
Application: 06/259,362 →
Method of Forming Self-Aligned Contact in Semiconductor Devices
Patent: 4,353,159 →
Application: 06/262,620 →
Device for Multisample Infrared Analysis of Materials in Microgram Quantity
Patent: 4,399,361 →
Application: 06/268,283 →
Multi-Layer Passivant System
Patent: 4,420,765 →
Application: 06/268,284 →
Method for Enhancing Electron Mobility in Gaas
Patent: 4,383,869 →
Application: 06/273,303 →
Method of Forming Tapered Contact Holes for Integrated Circuit Devices
Patent: 4,363,830 →
Application: 06/276,012 →
Sanitary Napkin with Disposal Means
Patent: 4,380,450 →
Application: 06/276,917 →
Optical Measurements of Fine Line Parameters in Integrated Circuit Processes
Patent: 4,408,884 →
Application: 06/278,448 →
Crossover Dielectric Inks
Patent: 4,369,254 →
Application: 06/280,916 →
Conductor Inks
Patent: 4,376,725 →
Application: 06/280,917 →
Overglaze Inks
Patent: 4,377,642 →
Application: 06/280,920 →
Low Value Resistor Inks
Patent: 4,379,195 →
Application: 06/280,937 →
Method of Making Electrically Programmable Control Gate Injected Floating Gate Solid State Memory Transistor
Patent: 4,332,077 →
Application: 06/284,106 →
Method of Forming Closely Spaced Lines or Contacts in Semiconductor Devices
Patent: 4,402,128 →
Application: 06/284,728 →
Offset Compensation Apparatus for Biasing an Analog Comparator
Patent: 4,417,160 →
Application: 06/288,626 →
Frequency-Controlled Variable-Gain Amplifiers
Patent: 4,429,285 →
Application: 06/288,686 →
Reactive Sputter Etching of Auminum
Patent: 4,387,013 →
Application: 06/295,513 →
Method for Determining Oxygen Content in Semiconductor Material
Patent: 4,429,047 →
Application: 06/297,176 →
Method and Apparatus for Determining the Doping Profile in Epitaxial Layers of Semiconductors
Patent: 4,456,879 →
Application: 06/298,581 →
Apparatus for Electrically Joining the Ends of Substantially Parallel Semiconductor Lines
Patent: 4,589,008 →
Application: 06/299,344 →
Ion Implanter End Processing Station
Patent: 4,405,864 →
Application: 06/300,118 →
Single Chip Microcomputer with External Decoder and Memory and in- Ternal Logic for Disabling the Rom and Felocating the Ram
Patent: 4,450,524 →
Application: 06/304,785 →
Circuitry for Generating Non-Overlapping Pulse Trains
Patent: 4,456,837 →
Application: 06/311,512 →
Actively Controlled Input Buffer
Patent: 4,437,024 →
Application: 06/313,660 →
Electronic Circuits and Structures Employing Enhancement and Depletion Type Igfets
Patent: 4,463,273 →
Application: 06/314,849 →
Fast Switching Transistor
Patent: 4,460,913 →
Application: 06/316,660 →
Method of Formimg Pattern in Positive Resist Media
Patent: 4,396,702 →
Application: 06/320,015 →
Method of Plasma Etching a Substrate
Patent: 4,357,369 →
Application: 06/320,016 →
Differential Current Amplifier
Patent: 4,429,283 →
Application: 06/320,434 →
Fixture for Testing Semiconductor Devices
Patent: 4,460,868 →
Application: 06/322,002 →
Operational Amplifier
Patent: 4,429,284 →
Application: 06/324,059 →
Switching Circuitry as for a Flash a/D Converter
Patent: 4,449,118 →
Application: 06/326,153 →
Implementation of Instruction for a Branch Which Can Cross One Page Boundary
Patent: 4,449,185 →
Application: 06/326,162 →
Porcelain Coated Metal Boards Having Interconnections Between the Face and Reverse Surfaces Thereof
Patent: 4,393,438 →
Application: 06/328,435 →
Sense Amplifiers
Patent: 4,434,381 →
Application: 06/328,437 →
A Method of Forming Resist Patterns Using X-Rays or Electron Beam
Patent: 4,397,938 →
Application: 06/330,492 →
A Method of Using a Positive Electron Beam Resist Medium
Patent: 4,397,939 →
Application: 06/330,579 →
Freeze Clock Circuit
Patent: 4,489,422 →
Application: 06/332,831 →
Self-Extinguishing Load Driving System
Patent: 4,441,069 →
Application: 06/334,818 →
Transparent Conductive Film Having Areas of High and Low Resistivity
Patent: 4,395,467 →
Application: 06/335,707 →
Transparent Conductive Film
Patent: 4,399,194 →
Application: 06/335,708 →
Plasma Etching of Polyimide
Patent: 4,357,203 →
Application: 06/335,852 →
Electromagnetic Radiation Annealing of Semiconductor Material
Patent: 4,439,245 →
Application: 06/342,473 →
Aqueous Developable Poly(Olefin Sulfone) Terpolymers
Patent: 4,393,160 →
Application: 06/347,107 →
Method for Detecting Distance Deviations to a Phtoresist Surface in an Optical Printer
Patent: 4,498,775 →
Application: 06/349,515 →
Method for the Manufacturing a Vertical Grooved Mosfet
Patent: 4,374,455 →
Application: 06/351,250 →
Push-Pull Non-Complementary Transistor Amplifier
Patent: 4,442,409 →
Application: 06/352,179 →
Method for Growing a Low Defect Monocrystalline Layer on a Mask
Patent: 4,482,422 →
Application: 06/352,883 →
Speed Up Circuit
Patent: 4,450,371 →
Application: 06/359,434 →
Plasma Etching of Aluminum
Patent: 4,372,807 →
Application: 06/362,041 →
Anisotropic Etching of Aluminum
Patent: 4,370,196 →
Application: 06/362,043 →
Plasma Etching of Aluminum
Patent: 4,375,385 →
Application: 06/362,044 →
Memory System with Redundancy for Error Avoidance
Patent: 4,464,754 →
Application: 06/362,462 →
Memory System with Error Detection and Correction
Patent: 4,464,755 →
Application: 06/362,463 →
Memory System with Error Storage
Patent: 4,472,805 →
Application: 06/362,464 →
Two Level Parity Error Correction System
Patent: 4,450,562 →
Application: 06/362,465 →
Apparatus for Electrophoretic Deposition
Patent: 4,376,031 →
Application: 06/363,801 →
Crossover Dielectric Inks Used in Forming a Multilayer Electrical Circuit
Patent: 4,369,220 →
Application: 06/374,967 →
Controlled Environment for Diffusion Furnace
Patent: 4,436,509 →
Application: 06/376,572 →
Selective Etching of Phosphosilicate Glass
Patent: 4,395,304 →
Application: 06/377,001 →
Doped-Oxide Diffusion of Phosphorus Using Borophosphosilicate Glass
Patent: 4,433,008 →
Application: 06/377,197 →
Low Temperature Elevated Pressure Glass Flow/Re-Flow Process
Patent: 4,420,503 →
Application: 06/379,103 →
Fet Negative Resistance Circuits
Patent: 4,491,807 →
Application: 06/380,289 →
Trimming Circuits for Precision Amplifier
Patent: 4,462,002 →
Application: 06/381,733 →
Structural Defect Detection
Patent: 4,436,999 →
Application: 06/386,240 →
Low Resistance Contact for High Density Integrated Circuit
Patent: 4,445,270 →
Application: 06/390,782 →
Epoxy Encapsulating Formulation
Patent: 4,401,775 →
Application: 06/391,923 →
Process for Forming an Improved Silicon-on-Sapphire Device
Patent: 4,496,418 →
Application: 06/393,616 →
Overglaze Inks
Patent: 4,401,709 →
Application: 06/396,661 →
Conductor Inks
Patent: 4,399,320 →
Application: 06/396,662 →
Positive Radiation Sensitive Resist Terpolymer from Omega Alkynoic Acid
Patent: 4,405,776 →
Application: 06/396,663 →
Bidirectional Interface
Patent: 4,471,243 →
Application: 06/401,625 →
Timing Circuit
Patent: 4,487,125 →
Application: 06/405,451 →
Output Protection Circuit for Preventing a Reverse Current
Patent: 4,471,237 →
Application: 06/407,897 →
High Speed Sense Amplifier
Patent: 4,521,703 →
Application: 06/412,807 →
Mosfet with Perimeter Channel
Patent: 4,532,534 →
Application: 06/415,486 →
Protection Circuit for Integrated Circuit Devices
Patent: 4,484,244 →
Application: 06/421,517 →
Monitor for Impurity Levels in Aluminum Deposition
Patent: 4,440,799 →
Application: 06/435,971 →
Automatic Liquid Dispensing Apparatus for Spinning Surface of Uniform Thickness
Patent: 4,451,507 →
Application: 06/437,835 →
Method to Determine the Crystalline Properties of an Interface of Two Materials by an Optical Technique
Patent: 4,498,772 →
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Dry Developable Positive Photoresists
Patent: 4,433,044 →
Application: 06/441,682 →
Detection Circuitry
Patent: 4,529,892 →
Application: 06/443,925 →
Coincident Pulse Cancelling Circuit
Patent: 4,502,014 →
Application: 06/444,164 →
Level Shift Interface Circuit
Patent: 4,501,978 →
Application: 06/444,459 →
Etching of Tantalum Silicide/Doped Polysilicon Structures
Patent: 4,411,734 →
Application: 06/448,279 →
Electrically Alterable, Nonvolatile Floating Gate Memory Device
Patent: 4,513,397 →
Application: 06/448,690 →
Semiconductor Device with Internal Gettering Region
Patent: 4,716,451 →
Application: 06/448,724 →
Transient Signal Suppression Circuit
Patent: 4,525,635 →
Application: 06/450,062 →
Method of Forming Metal Lines
Patent: 4,400,257 →
Application: 06/451,818 →
Air-Fireable Thick Film Inks
Patent: 4,415,624 →
Application: 06/455,310 →
Method of Making a Semiconductor Device to Improve Conductivity of Amorphous Silicon Films
Patent: 4,472,210 →
Application: 06/456,493 →
Deposition of Silicon Dioxide
Patent: 4,686,112 →
Application: 06/457,578 →
Indium Oxide Resistor Inks
Patent: 4,467,009 →
Application: 06/459,754 →
Low Value Resistor Inks
Patent: 4,452,844 →
Application: 06/460,008 →
Method of Forming a Self Aligned Aluminum Polycrystalline Silicon Line
Patent: 4,433,469 →
Application: 06/466,593 →
Apparatus for Spraying a Liquid on a Spinning Surface
Patent: 4,457,259 →
Application: 06/475,035 →
Chemical Deposition Termination
Patent: 4,442,134 →
Application: 06/476,781 →
Method for Mounting a Sapphire Chip on a Metal Base and Article Produced Thereby
Patent: 4,457,976 →
Application: 06/479,518 →
Programmable Logic Gates and Networks
Patent: 4,495,427 →
Application: 06/480,596 →
Reverse Etching of Chromium
Patent: 4,421,593 →
Application: 06/483,876 →
Lid Latching Apparatus
Patent: 4,476,994 →
Application: 06/484,525 →
Memory System
Patent: 4,558,435 →
Application: 06/499,397 →
Cmos Structure Incorporating Vertical Igfets
Patent: 4,566,025 →
Application: 06/503,044 →
Linear Sense Amplifier
Patent: 4,567,387 →
Application: 06/509,787 →
Process for Radiation Free Electron Beam Deposition
Patent: 4,472,453 →
Application: 06/510,174 →
Method for Grounding a Pellet Support Pad in an Integrated Circuit Device
Patent: 4,534,105 →
Application: 06/521,897 →
Electrically Alterable Programmable Nonvolatile Floating Gate Memory Device
Patent: 4,608,591 →
Application: 06/523,921 →
Priority Encoded Spare Element Decoder
Patent: 4,639,897 →
Application: 06/528,035 →
Method and Apparatus for Implanation of Doubly-Charged Ions
Patent: 4,560,879 →
Application: 06/532,899 →
Sipos Deposition Method
Patent: 4,489,103 →
Application: 06/532,973 →
Fast Switching Circuit
Patent: 4,532,436 →
Application: 06/537,817 →
Local Oxidation of Silicon Substrate Using Lpcvd Silicon Nitride
Patent: 4,472,459 →
Application: 06/545,048 →
Multiple Connection Bond Pad for an Integrated Circuit Device and Method of Making Same
Patent: 4,558,345 →
Application: 06/546,181 →
Surface Preparation for Determining Diffusion Length by the Surface Photovoltage Method
Patent: 4,507,334 →
Application: 06/547,012 →
Method for Revealing Semiconductor Surface Damage Using Surface Damage Using Surface Photovoltage (Spv) Measurements
Patent: 4,567,431 →
Application: 06/547,326 →
Method of Forming Semiconductor Contacts by Implanting Ions of Neutral Species at the Interfacial Region
Patent: 4,502,206 →
Application: 06/553,255 →
Method for Growing Monocrystalline Silicon on a Mask Layer
Patent: 4,549,926 →
Application: 06/553,305 →
Bias Network Having One Mode for Producing a Regulated Output
Patent: 4,567,381 →
Application: 06/556,931 →
Distributor Tube for Cvd Reactor
Patent: 4,499,853 →
Application: 06/559,720 →
Method of Fabricating High Speed Cmos Devices
Patent: 4,519,126 →
Application: 06/560,459 →
Electrical Connector
Patent: 4,478,472 →
Application: 06/561,272 →
Ttl Circuit with a Clamping Transistor for Speedy Turn- Off of Output Transistor
Patent: 4,631,422 →
Application: 06/562,529 →
Fatterning of Submicrometer Metal Silicide Structures
Patent: 4,460,435 →
Application: 06/562,530 →
Selective Semiconductor Coating and Protective Mask Therefor
Patent: 4,612,211 →
Application: 06/563,627 →
Preparation of Organic Layers for Oxygen Etching
Patent: 4,470,871 →
Application: 06/565,338 →
Auto Ranging Counter
Patent: 4,546,487 →
Application: 06/567,336 →
Dielectric Layers in Multilayer Refractory Metallization Structure
Patent: 4,582,745 →
Application: 06/571,423 →
Regulator for Bias Current of Semiconductor Laser Diode
Patent: 4,484,331 →
Application: 06/572,955 →
Method of Making Vertical Mosfet with Reduced Bipolar Effects
Patent: 4,587,713 →
Application: 06/582,601 →
Method of Forming Self-Aligned Contact Openings
Patent: 4,512,073 →
Application: 06/582,752 →
Method Using Surface Photovoltage (Spv) Measurements for Revealing Heavy Metal Contamination of Semiconductor Material
Patent: 4,598,249 →
Application: 06/584,814 →
Lpcvd Deposition of Tantalum Silicide
Patent: 4,504,521 →
Application: 06/592,397 →
Power Down Sensor
Patent: 4,594,517 →
Application: 06/605,241 →
Deep Ultraviolet (Duv) Flood Exposure System
Patent: 4,575,636 →
Application: 06/605,244 →
Deep Ultraviolet (Duv) Flood Exposure System
Patent: 4,625,120 →
Application: 06/605,245 →
Mosfet with Reduced Bipolar Effects
Patent: 4,639,762 →
Application: 06/605,427 →
Method for Growing Monocrystalline Silicon Through Mask Layer
Patent: 4,578,142 →
Application: 06/608,544 →
Switching Circuit
Patent: 4,614,897 →
Application: 06/609,360 →
Universal Interface Circuit for Microprocessor Peripherals
Patent: 4,641,261 →
Application: 06/612,427 →
Priority Arbitration Logic for a Multi-Master Bus System
Patent: 4,639,859 →
Application: 06/613,410 →
Analog-To-Digital Converters with Virtual Integration
Patent: 4,617,550 →
Application: 06/613,415 →
Reference Circuit with Semiconductor Memory Array
Patent: 4,648,074 →
Application: 06/625,910 →
Electrically Erasable Programmable Electronic Circuits Using Programmable-Threshold-Voltage Fet Pairs
Patent: 4,596,938 →
Application: 06/627,920 →
Voltage Level Sensing Circuit
Patent: 4,594,518 →
Application: 06/628,302 →
Diode Structure
Patent: 4,589,002 →
Application: 06/631,869 →
Electrically Alterable, Nonvolatile Floating Gate Memory Device
Patent: 4,618,876 →
Application: 06/633,188 →
Ion-Implantation of Phosphorous, Arsenic or Boron by Pre-Amorphizing with Fluorine Ions
Patent: 4,584,026 →
Application: 06/634,397 →
Deposition of Borophosphosilicate Glass
Patent: 4,546,016 →
Application: 06/636,832 →
Semiconductor Structure for Electric Field Distribution
Patent: 4,605,948 →
Application: 06/637,027 →
Reusable Centrifuge Fixture and Methods of Making and Using Same
Patent: 4,586,375 →
Application: 06/645,217 →
High-Speed Output Driver
Patent: 4,612,466 →
Application: 06/646,102 →
Neutralization of Acceptor Levels in Silicon by Atomic Hydrogen
Patent: 4,584,028 →
Application: 06/653,559 →
Anisotropic Etching of Aluminum
Patent: 4,547,261 →
Application: 06/655,692 →
Gate Shield Structure for Power Mos Device
Patent: 4,631,564 →
Application: 06/664,027 →
Gray Code Counter
Patent: 4,618,849 →
Application: 06/666,721 →
Anti-Vibration System
Patent: 4,643,385 →
Application: 06/671,917 →
High-Speed Voltage Level Shift Circuit
Patent: 4,656,373 →
Application: 06/674,845 →
Bit-Line Pull-Up Circuit
Patent: 4,639,898 →
Application: 06/685,251 →
Low Temperature Growth of Silicon Dioxide on Silicon
Patent: 4,576,829 →
Application: 06/687,366 →
Method for Forming Uniformly Thick Selective Epitaxial Silicon
Patent: 4,592,792 →
Application: 06/694,100 →
Reactive Sputter Etching of Metal Slicide Structures
Patent: 4,608,118 →
Application: 06/702,338 →
Vertical Mosfet with Diminished Bipolar Effects
Patent: 4,639,754 →
Application: 06/705,371 →
Circuit and Structure for Protecting Integrated Circuits from Destructive Transient Voltages
Patent: 4,633,283 →
Application: 06/710,271 →
Formation of Conductive Lines
Patent: 4,585,515 →
Application: 06/710,284 →
Two-Layer Negative Resist
Patent: 4,612,270 →
Application: 06/711,720 →
Crossunders for High Density Sos Integrated Circuits
Patent: 4,575,746 →
Application: 06/712,479 →
Method for Making Semiconductor Device with Integral Fuse
Patent: 4,598,462 →
Application: 06/715,039 →
Analog-To-Digital Converter with Scaling of Input Signal
Patent: 4,641,130 →
Application: 06/717,827 →
Precision Setting of the Bias Point of an Amplifying Means
Patent: 4,594,560 →
Application: 06/724,245 →
Diamond-Like Film
Patent: 4,603,082 →
Application: 06/728,588 →
Method for Thinning Silicon
Patent: 4,615,762 →
Application: 06/729,165 →
Method of Laser Soldering
Application: 06/730,444 →
Zener Diode Structure
Patent: 4,631,562 →
Application: 06/739,820 →
Dual Inverse Zener Diode with Buried Junctions
Patent: 4,651,178 →
Application: 06/739,911 →
Absorptive Layer for Optical Lithography
Patent: 4,618,565 →
Application: 06/741,358 →
Protection Circuit for Integrated Circuit Devices
Patent: 4,595,941 →
Application: 06/741,703 →
In-Situ Cleaned Ohmic Contacts
Patent: 4,605,479 →
Application: 06/748,350 →
Process of Using Absorptive Layer in Optical Lithography with Over- Lying Photoresist Layer to Form Relief Pattern on Substrate
Patent: 4,609,614 →
Application: 06/748,355 →
Vertical Igfet with Internal Gate and Method for Making Same
Patent: 4,586,240 →
Application: 06/748,940 →
Clock Synchronization Circuit for a Computer Timer
Patent: 4,689,575 →
Application: 06/755,012 →
Fast Ternary (Gainas) Logic Gate Device
Patent: 4,639,752 →
Application: 06/755,828 →
Automatic Pin Extraction Apparatus for Integrated Circuit Tube
Patent: 4,620,366 →
Application: 06/755,915 →
Method of Forming Multi-Level Metallization
Patent: 4,662,064 →
Application: 06/762,521 →
Method of Making a Mos Field Effect Transistor in an Integrated Circuit
Patent: 4,660,276 →
Application: 06/764,551 →
Absorptive Planarizing Layer for Optical Lithography
Patent: 4,621,042 →
Application: 06/766,285 →
Method for Fabricating a Radiation Hardened Oxide Having Two Portions
Patent: 4,675,978 →
Application: 06/773,771 →
Method for Fabricating a Radiation Hardened Oxide Having Structural Damage
Patent: 4,634,473 →
Application: 06/773,772 →
Method for Preventing Arcing in a Device During Ion-Implantation
Patent: 4,595,837 →
Application: 06/775,942 →
Method of Making Stabilized Silicon-on-Insulator Field-Effect Transistors Having 100 Oriented Side and Top Surfaces
Patent: 4,662,059 →
Application: 06/777,584 →
Profile Control of Boron Implant
Patent: 4,637,836 →
Application: 06/778,986 →
Silicon-On-Sapphire Integrated Circuit and Method of Making the Same
Patent: 4,751,554 →
Application: 06/780,897 →
Digital Timing System
Patent: 4,638,498 →
Application: 06/780,898 →
Insulated Gate Device
Patent: 4,809,045 →
Application: 06/781,381 →
Insulated Gate Device
Patent: 4,682,195 →
Application: 06/781,383 →
Optical Profilometer for Steep Surface Contours with Significant Surface Tilt
Patent: 4,579,454 →
Application: 06/783,268 →
Method for Increasing the Switching Speed of a Semiconductor Device by Neutron Irradiation
Patent: 4,684,413 →
Application: 06/784,726 →
Apparatus for Holding a Part in a Wave Soldering Machine
Patent: 4,614,294 →
Application: 06/792,473 →
Spin-Coating Procedure
Patent: 4,741,926 →
Application: 06/792,535 →
Lift-Off Technique for Producing Metal Pattern Using Single Photo- Resist Processing and Oblique Angle Metal Deposition
Patent: 4,687,730 →
Application: 06/792,790 →
Switchable Oscillator Circuit
Patent: 4,613,829 →
Application: 06/793,237 →
System for Determining Time Duration of Angular Rotation
Patent: 4,642,772 →
Application: 06/793,311 →
Method to Inhibit Autodoping in Epitaxial Layers from Heavily Doped Substrates in Cvd Processing
Patent: 4,661,199 →
Application: 06/797,126 →
Integrated Circuit Device Having Slanted Peripheral Circuits
Patent: 4,789,889 →
Application: 06/799,825 →
Treatment of Planarizing Layer in Multilayer Electron Beam Resist
Patent: 4,702,993 →
Application: 06/802,020 →
Method of Depositing Uniformly Thick Selective Epitaxial Silicon
Patent: 4,698,316 →
Application: 06/802,994 →
Method and Apparatus for Forming Large Area High Resolution Patterns
Patent: 4,668,080 →
Application: 06/803,006 →
Level Shift Circuit Including Source Follower Output
Patent: 4,695,744 →
Application: 06/809,132 →
Control of Signal Transmission
Patent: 4,882,749 →
Application: 06/817,489 →
Apparatus and Method for Producing Ions
Patent: 4,697,085 →
Application: 06/823,257 →
Apparatus and Method for Producing Ions
Patent: 4,691,109 →
Application: 06/823,258 →
Orthogonal Bipolar Transistor
Patent: 4,792,837 →
Application: 06/833,074 →
Overvoltage Comparator
Patent: 4,654,545 →
Application: 06/834,386 →
Comparator Circuit
Patent: 4,680,483 →
Application: 06/834,387 →
Cfet Inverter Having Equal Output Signal Rise and Fall Times by Adjustment of the Pull--- Up and -Down Transconductances
Patent: 4,682,055 →
Application: 06/839,917 →
Epitaxial Metal Silicide Layers
Patent: 4,687,537 →
Application: 06/852,290 →
Method for Forming Dielectrically Isolated Pmos, Nmos, Pnp and Npn Transistors on a Silicon Wafer
Patent: 4,685,199 →
Application: 06/857,154 →
Integrated Circuits with Electrically Erasable Electrically Programmable Latch Circuits Therein for Controlling Operation
Patent: 4,652,773 →
Application: 06/858,024 →
Overlay Applying Press
Patent: 4,704,183 →
Application: 06/863,078 →
Bidirectional Vertical Power Mos Device and Fabrication Method
Patent: 4,641,164 →
Application: 06/868,633 →
Method of Forming Isolation Regions in a Semiconductor Device
Patent: 4,692,992 →
Application: 06/878,259 →
Test Mask for Determining Alignment of an Automatic Ic Mask Testing Apparatus
Patent: 4,710,440 →
Application: 06/885,165 →
High Current Lateral Transistor Structure
Patent: 4,684,970 →
Application: 06/885,744 →
Constant Current Load and Level Shifter Circuitry
Patent: 4,731,589 →
Application: 06/889,209 →
Cmos Input Level Shifting Buffer Circuit
Patent: 4,707,623 →
Application: 06/890,275 →
Method of Forming Tapered Contact Openings
Patent: 4,698,132 →
Application: 06/913,325 →
Integrated Lateral Pnp Transistor and Current Limiting Resistor
Patent: 4,785,339 →
Application: 06/915,985 →
Bidirectional Vertical Power Mos Device and Fabrication Method
Patent: 4,700,460 →
Application: 06/924,865 →
Constant Ratio, Size Insensitive, Capacitor Structure
Patent: 4,695,922 →
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Decoder Circuitry with Reduced Number Inverters and Bus Lines
Patent: 4,758,744 →
Application: 06/935,389 →
Apparatus and Method for Maintaining a Uniform Etching Solution Composition
Patent: 4,710,261 →
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Dielectrically Isolated Pmos, Nmos, Pnp and Npn Transistors on a Silicon Wafer
Patent: 4,751,561 →
Application: 07/033,378 →
Switched Capacitor Filter for Use with a Digital-to-Analog (D/a) Converter
Patent: 4,968,989 →
Application: 07/040,168 →
Edgeless Semiconductor Device
Application: 07/048,706 →
Cmos Voltage Divider Circuits
Patent: 4,847,518 →
Application: 07/120,422 →
Ion Implantation Method and Apparatus
Patent: 4,881,010 →
Application: 07/148,209 →
Analog to Digital Converter with Integral Linearity Error Compensation and Method of Operation
Patent: 4,924,225 →
Application: 07/149,514 →
High Speed Apparatus for a Single Latch Flash Analog-to-Digital Converter
Patent: 4,897,655 →
Application: 07/166,483 →
Decoder Error Prevention Apparatus for Use in Flash Analog-to-Digital Converters
Patent: 5,023,613 →
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Truncated Product Partial Canonical Signed Digit Multiplier
Patent: 4,967,388 →
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Digital Filter Employing Parallel Processing
Patent: 4,947,362 →
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Electrostatic Field Generator for Liquid Treatment
Patent: 4,822,473 →
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Transistor Base Current Compensation Circuitry
Patent: 4,924,113 →
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Optoelectronic System for Determining Surface Irregularities of a Workpiece Having a Nominally Plane Reflective
Patent: 5,003,615 →
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Precision Temperature-Stable Current Sources/Sinks
Patent: 4,853,610 →
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Symmetrical Variable Impedance Apparatus Employing Mos Transistors
Patent: 5,021,747 →
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Power Mosfet Transistor Circuit
Patent: 5,023,692 →
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Two Dimensional Hybrid Digital Convolver
Patent: 4,998,288 →
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High Current Hermetic Package
Patent: 5,148,264 →
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Heat Sink and Multi Mount Pad Lead Frame Package and Method for Electrically Isolating Semiconductor Die(S)
Patent: 5,049,973 →
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Hermetically Sealed Die Package with Floating Source
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Power Mosfet with an Anode Region
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Related Assignments (7)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. Dec 7, 1981
From: STEWART, ROGER G.
To: RCA CORPORATION
Reel/Frame 003964/0393 →
Assignment of Assignors Interest. Apr 30, 1985
From: JASTRZEBSKI, LUBOMIR L.; CORBOY, JOHN F. JR.; PAGLIARO, ROBERT H. JR.; SOYDAN, RAMAZAN
To: RCA CORPORATION, A CORP. OF DE.
Reel/Frame 004428/0560 →
Assignment of Assignors Interest. May 6, 1985
From: SCHNABLE, GEORGE L.; ZANZUCCHI, PETER J.
To: RCA CORPORATION
Reel/Frame 004408/0660 →
Assignment of Assignors Interest. May 31, 1985
From: AVERY, LESLIE R.
To: RCA CORPORATION
Reel/Frame 004412/0664 →
Security Interest Nov 8, 1999
From: INTERSIL CORPORATION
To: CREDIT SUISSE FIRST BOSTON, AS COLLATERAL AGENT
Reel/Frame 010351/0410 →
Intellectual Property Partial Release Mar 16, 2001
From: CREIDT SUISSE FIRST BOSTON
To: INTERSIL HOLDING CORPORATION
Reel/Frame 011667/0166 →
Reassignment of Patent Applications Jul 16, 2001
From: INTERSIL CORPORATION
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 012002/0206 →