IP Library › Assignment 010247/0043
Patent Assignment
Reel/Frame 010247/0043

Assignment of Assignor's Interest

Recorded: 1999-09-27 Pages: 14
Assignor
HARRIS CORPORATION
Executed: 1999-08-13
Assignee
INTERSIL CORPORATION
2401 PALM BAY ROAD, N.E., PALM BAY, FLORIDA, 32905
Covered Properties (612)
Radiation Hard, High Emitter-Base Breakdown Bipolar Transistor
Patent: 4,881,111 →
Application: 05/973,822 →
Method of Fabricating Lateral Pnp Transistors Ulizing Selective Diffusion and Counter Doping
Patent: 4,283,236 →
Application: 06/077,234 →
Vertical Fuse and Method of Fabrication
Patent: 4,312,046 →
Application: 06/081,978 →
Complementary Igfet Buffer with Improved Bipolar Output
Patent: 4,301,383 →
Application: 06/082,185 →
Programmable Threshold Switchables Resistive Memory Cell Array
Patent: 4,236,231 →
Application: 06/082,505 →
Two Switchable Resistive Element Per Cell Memory Array
Patent: 4,272,833 →
Application: 06/082,506 →
Method for Qualifying Biased Integrated Circuits on a Wafer Level
Patent: 4,288,911 →
Application: 06/106,127 →
Method of Making Schottky Barrier Diode by Ionimplantation and Impurity Diffusion
Patent: 4,260,431 →
Application: 06/106,128 →
Method for Qualifying Biased Burn-in Integrated Circuits on a Wafer Level
Patent: 4,281,449 →
Application: 06/106,339 →
Low Thermal Coefficient Semiconductor Device
Patent: 4,319,257 →
Application: 06/112,618 →
System for Short Circuit Protection Using Electronic Logic in a Feed Back Arrangement
Patent: 4,305,106 →
Application: 06/113,430 →
Fabrication of Complementary Bipolar Transistors and Cmos Devices with Poly Gates
Patent: 4,299,024 →
Application: 06/124,201 →
Method of Fabricating Mesa Bipolar Memory Cell Utilizing Epitaxial Deposition, Substrate Removal and Special Metallization
Patent: 4,292,730 →
Application: 06/129,913 →
Method of Solder Reflow Assembly
Patent: 4,334,646 →
Application: 06/141,100 →
Method of Fabricating Surface Contacts for Buried Layer into Dielectric Isolated Islands
Patent: 4,290,831 →
Application: 06/141,504 →
Method of Serialization of Dice
Patent: 4,409,686 →
Application: 06/159,750 →
Differential Linear to Digital Translator
Patent: 4,368,395 →
Application: 06/170,291 →
Radiation Hardened-Self Aligned Cmos and Method of Fabrication
Patent: 4,402,002 →
Application: 06/190,515 →
Fabrication of Isolated Regions for Use in Self - Aligning Device Process Utilizing Selective Oxidation
Patent: 4,670,769 →
Application: 06/200,386 →
Mask Alignment Scheme for Laterally and Totally Dielectrically Isolated Integrated Circuits
Patent: 4,309,813 →
Application: 06/212,799 →
Amorphous Devices and Interconnect System and Method of Fabrication
Patent: 4,471,376 →
Application: 06/224,931 →
Ttl to Cmos Interface Circuit
Patent: 4,380,710 →
Application: 06/231,671 →
Cmos Amplifier
Patent: 4,446,444 →
Application: 06/231,672 →
Reversibly Programmable Polycrystalline Silicon Memory Element
Patent: 4,420,766 →
Application: 06/232,520 →
Integrated Ram/Earom Memory System
Patent: 4,402,065 →
Application: 06/242,658 →
Time-Division Multiplex Serial Loop
Patent: 4,389,721 →
Application: 06/278,990 →
Miniature Resistive Temperature Detector and Method of Fabrication
Patent: 4,462,020 →
Application: 06/296,191 →
Transistor Circuit for Reducing Gate Leakage Current in a Jfet
Patent: 4,472,648 →
Application: 06/296,192 →
Power Efficient Ttl Buffer for Driving Large Capacitive Loads
Patent: 4,454,432 →
Application: 06/300,617 →
Circuit Design Technique to Prevent Current Hogging When Minimizing Interconnect Stripes by Paralleling Stl or Isl Gate Inputs
Patent: 4,682,057 →
Application: 06/301,761 →
Vertical Fuse and Method of Fabrication
Patent: 4,403,399 →
Application: 06/306,226 →
Isolated Gate Jfet Structure
Patent: 4,456,918 →
Application: 06/309,194 →
Kelvin-Connected Buried Zener Voltage Reference Circuit
Patent: 4,398,142 →
Application: 06/310,035 →
Circuit for Trimming Fet Differential Pair Offset Voltage Without Increasing the Offset Voltage Temperature Coefficient
Patent: 4,464,631 →
Application: 06/326,345 →
High Temperature Bias Line Stabilized Current Sources
Patent: 4,471,236 →
Application: 06/351,442 →
High Temperature Current Mirror Amplifier
Patent: 4,450,414 →
Application: 06/351,443 →
Rom/Pla Structure and Method of Testing
Patent: 4,461,000 →
Application: 06/353,604 →
Integrated Program Counter Memory Management Register and Incrementer
Patent: 4,514,802 →
Application: 06/363,815 →
Phase-To-Voltage Converter
Patent: 4,480,219 →
Application: 06/372,812 →
Pulsed Linear Integrated Circuit Tester
Patent: 4,528,504 →
Application: 06/382,603 →
Slic Ii - Common Mode Current Rejection
Patent: 4,524,246 →
Application: 06/396,072 →
Method of Fabrication Bipolar Transistor with Improved Base Collector Breakdown Voltage and Collector Series Resistance
Patent: 4,532,003 →
Application: 06/406,333 →
Integrated Circuit Switch Using Stacked Scrs
Patent: 4,528,461 →
Application: 06/414,862 →
Cache Memory Flush Scheme
Patent: 4,567,578 →
Application: 06/416,034 →
Voltage Equalizer Bridge
Patent: 4,401,940 →
Application: 06/431,229 →
Method for Providing Polysilicon Thin Films of Improved Uniformity
Patent: 4,466,179 →
Application: 06/435,221 →
I2L Structure and Fabrication Process Compatible with High Voltage Bipolar Transistors
Patent: 4,546,539 →
Application: 06/447,946 →
Formant-Based Speech Synthesizer
Patent: 4,586,193 →
Application: 06/447,947 →
A. C. Testing of Logic Arrays
Patent: 4,503,387 →
Application: 06/454,533 →
Integrated Circuit Switch Using Stacked Scrs
Patent: 4,528,462 →
Application: 06/460,020 →
Arithmetic Logic Unit
Patent: 4,559,608 →
Application: 06/460,061 →
Process for Fabrication of High-Speed Radiation Hard Bipolar Semiconductor Devices
Patent: 4,464,825 →
Application: 06/467,295 →
Address Decoder
Patent: 4,581,548 →
Application: 06/475,618 →
Controlled Current Limiter
Patent: 4,495,537 →
Application: 06/493,234 →
Binarily Weighted D to a Converter Ladder with Inherently Reduced Ladder Switching Noise
Patent: 4,580,131 →
Application: 06/500,910 →
High Voltage Current Mirror
Patent: 4,532,481 →
Application: 06/504,312 →
Reduction of Series Propagation Delay and Impedance
Patent: 4,584,660 →
Application: 06/506,793 →
Power Switched Logic Gates
Patent: 4,567,385 →
Application: 06/506,794 →
Method of Fabricating Low Noise Reference Diodes and Transistors
Patent: 4,590,664 →
Application: 06/518,598 →
Dielectric Isolation Fabrication for Laser Trimming
Patent: 4,468,414 →
Application: 06/518,725 →
Speech Data Econding Scheme
Patent: 4,703,505 →
Application: 06/526,065 →
Method of Determining Position on a Wafer
Patent: 4,566,796 →
Application: 06/526,066 →
Process for Minimizing Boron Depletion in N-Channel Fet at the Silicon-Silicon Oxide Interface
Patent: 4,596,068 →
Application: 06/566,400 →
High Density Packaging Technique for Electronic Systems
Patent: 4,631,636 →
Application: 06/593,516 →
Current Compensation for Logic Gates
Patent: 4,613,772 →
Application: 06/598,985 →
Method of Fabricating an Isolated Gate Jfet
Patent: 4,495,694 →
Application: 06/599,817 →
Laser Trimming of Resistors Over Dielectrically Isolated Islands
Patent: 4,594,265 →
Application: 06/610,583 →
Polysilicon Thin Films of Improved Electrical Uniformity
Patent: 4,536,231 →
Application: 06/612,877 →
Grey Code Dac Ladder
Patent: 4,591,826 →
Application: 06/620,728 →
A Process of Making Twin Will Vlsi Cmos
Patent: 4,599,789 →
Application: 06/620,835 →
Current to Voltage Interface
Patent: 4,665,327 →
Application: 06/625,222 →
Circuit for Increasing Voltage Gain
Patent: 4,560,948 →
Application: 06/630,280 →
Implant Mask Reversal Process
Patent: 4,578,859 →
Application: 06/643,362 →
Differential Input Stage for the Realization of Low Noise and High Precision Bipolar Transistor Amplifiers
Patent: 4,639,684 →
Application: 06/668,864 →
Method for Selective Deposition of Tungsten on Silicon
Patent: 4,595,608 →
Application: 06/669,787 →
Programmable Current Mirror
Patent: 4,608,530 →
Application: 06/669,788 →
Cmos Power-Up Reset Circuit for Gate Arrays and Standard Cells
Patent: 4,633,107 →
Application: 06/673,386 →
Monolithic Transient Protector
Patent: 4,618,743 →
Application: 06/675,222 →
Redundant Row Decoding for Programmable Devices
Patent: 4,639,896 →
Application: 06/676,846 →
Electrochemical Dielectric Isolation Technique
Patent: 4,554,059 →
Application: 06/678,075 →
Alignment Target Image Enhancement for Microlithography Process
Patent: 4,632,557 →
Application: 06/694,096 →
Conductivity Modulated Semiconductor Structure
Patent: 4,694,313 →
Application: 06/702,601 →
Subcollector for Oxide and Junction Isolated Ic's
Patent: 4,644,383 →
Application: 06/720,679 →
Simultaneous Plasma Sculpturing and Dual Tapered Aperture Etch
Patent: 4,705,596 →
Application: 06/723,238 →
Photoresist Tapering Process
Patent: 4,705,597 →
Application: 06/723,239 →
Stress Free Dielectric Isolation Technology
Patent: 4,606,936 →
Application: 06/723,581 →
Ttl Compatible Cmos Input Buffer
Patent: 4,717,847 →
Application: 06/728,271 →
Bit Addressable Programming Arrangement
Patent: 4,719,598 →
Application: 06/739,843 →
Pulsed Linear Integrated Circuit Tester
Patent: 4,616,178 →
Application: 06/744,336 →
Direct Coupled Swithcing Power Supply with Gto Scr Switching Element
Patent: 4,675,798 →
Application: 06/754,711 →
Fuse Programmable Dc Level Generator
Patent: 4,686,384 →
Application: 06/763,861 →
Method of Ensuring Adhesion of Chemically Vapor Deposited Oxide to Gold Integrated Circuit Interconnect Lines
Patent: 4,716,071 →
Application: 06/768,326 →
Method for Successive Approximation a/D Conversion
Patent: 4,620,179 →
Application: 06/771,160 →
Electrodeposition of Submicrometer Metallic Interconnect for Integrated Circuits
Patent: 4,624,749 →
Application: 06/771,712 →
Method of Selectively Soldering the Underside of a Substrate Having Leads
Patent: 4,684,055 →
Application: 06/771,846 →
Ttl Compatible Input Buffer
Patent: 4,677,321 →
Application: 06/774,474 →
Ic Which Eliminates Support Bias Influence on Dielectrically Isolated Components
Patent: 4,807,012 →
Application: 06/777,269 →
Programmable Array Logic with Shared Product Terms
Patent: 4,644,191 →
Application: 06/777,685 →
Programmable Array Logic with Shared Product Terms and J-K Registered Outputs
Patent: 4,644,192 →
Application: 06/777,686 →
Zener Structures with Connections to Buried Layer
Patent: 4,652,895 →
Application: 06/782,192 →
Front End of an Operational Amplifier
Patent: 4,636,744 →
Application: 06/782,689 →
Front End Stage of an Operational Amplifier
Patent: 4,636,743 →
Application: 06/782,690 →
Process Using Tungsten for Multilevel Metallization
Patent: 4,650,696 →
Application: 06/782,691 →
Internally Synchronous Matrix Structure for Use in Externally Asynchronous Programmable Devices
Patent: 4,658,253 →
Application: 06/786,701 →
Fabrication of Vertical Npn and Pnp Bipolar Transistors in Monolithic Substrate
Patent: 4,665,425 →
Application: 06/787,927 →
Programming Arrangement for Programmable Devices
Patent: 4,734,885 →
Application: 06/788,585 →
Auxiliary Word Line Driver for Effectively Controlling Programmability of Fusible Links
Patent: 4,734,886 →
Application: 06/790,115 →
Variable Wavelength Optical Alignment System
Patent: 4,669,884 →
Application: 06/792,988 →
Comparator Input Stage for Interface with Signal Current
Patent: 4,682,059 →
Application: 06/793,316 →
Dense, Reduced Leakage Cmos Structure
Patent: 4,720,739 →
Application: 06/798,242 →
Conveyor for Vapor Phase Reflow System
Patent: 4,703,566 →
Application: 06/798,668 →
Technique for Increasing Gate-Drain Breakdown Voltage of Ion-Implanted Jfet
Patent: 4,683,485 →
Application: 06/813,718 →
Esd Protection Transistors
Patent: 4,760,433 →
Application: 06/824,870 →
Non-Contact I/O Signal Transmission in Integrated Circuit Packaging
Patent: 4,862,231 →
Application: 06/827,285 →
Via Metallization Using Metal Fillets
Patent: 4,666,737 →
Application: 06/828,186 →
High Voltage Lateral Mos Structure with Depleted Top Gate Region
Patent: 4,823,173 →
Application: 06/831,384 →
Technique for Elimination of Polysilicon Stringers in Direct Moat Field Oxide Structure
Patent: 4,702,000 →
Application: 06/841,297 →
Test Circuitry for Testing Fuse Link Programmable Memory Devices
Patent: 4,698,589 →
Application: 06/842,267 →
Test Enabling Circuit for Enabling Overhead Test Circuitry in Programmable Devices
Patent: 4,733,168 →
Application: 06/842,272 →
Multiple-Layer, Multiple-Phase Titanium/Nitrogen Adhesion/Diffusion Barrier Layer Structure for Gold-Base Microcircuit Interconnection
Patent: 4,702,967 →
Application: 06/874,393 →
High Voltage Ic Bipolar Transistors Operable to Bvcbo and Method of Fabrication
Patent: 4,729,008 →
Application: 06/883,279 →
Low Noise Current Spectral Density Input Bias Current Cancellation Scheme
Patent: 4,755,770 →
Application: 06/896,097 →
Low Power Sense Amplifier
Patent: 4,701,644 →
Application: 06/896,103 →
Logic State Transition Detection Circuit for Cmos Devices
Patent: 4,728,820 →
Application: 06/901,841 →
Thermally Coupled Information Transmission Across Electrical Isolation Boundaries
Patent: 4,757,528 →
Application: 06/903,785 →
Esd Protection Network for Igfet Circuits with Scr Prevention Guard Rings
Patent: 4,757,363 →
Application: 06/914,524 →
Front End Stage of an Operational Amplifier
Patent: 4,783,637 →
Application: 06/917,441 →
Dielectric for Laser Trimming
Patent: 4,708,747 →
Application: 06/919,465 →
Method of Enhancing Silicon Etching Capability of Alkali Hydroxide Through the Addition of Positive Valence Impurity Ions
Patent: 4,781,853 →
Application: 06/936,609 →
Regulator Circuit for Conventing Alternating Input to a Constant Direct Output
Patent: 4,754,388 →
Application: 06/944,399 →
Technique for Forming Electric Field Shielding Layer in Oxygen- Implanted Silicon Substrate
Patent: 4,786,608 →
Application: 06/947,749 →
Fabrication of Vertical Npn and Pnp Bipolar Transistors in Monolithic Substrate
Patent: 4,717,680 →
Application: 07/000,377 →
Process for Performing Variable Selectivity Polysilicon Etch
Patent: 4,789,426 →
Application: 07/000,778 →
Programmable Logic Device with Programmable Signal Inhibition and Inversion Means
Patent: 4,761,570 →
Application: 07/013,851 →
Method for Forming Planarized Interconnect Level Using Selective Deposition and Ion Implantation
Patent: 4,814,285 →
Application: 07/019,697 →
Double Level Conductor Structure
Patent: 5,066,995 →
Application: 07/025,435 →
Process for the Fabrication of a Vertical Contact
Patent: 4,851,257 →
Application: 07/025,539 →
Fast Voltage Reference Stabilization Circuit
Patent: 4,804,865 →
Application: 07/027,940 →
Area Feature Sorting Mechanism for Neighborhood-Based Proximity Correction in Lithography Processing of Integrated Circuit Patterns
Patent: 4,812,962 →
Application: 07/036,508 →
Using a Rapid Thermal Process for Manufacturing a Wafer Bonded Soi Semiconductor
Patent: 4,771,016 →
Application: 07/042,135 →
Method of Ensuring Adhesion of Chemically Vapor Deposited Oxide to Gold Integrated Circuit Interconnect Lines
Patent: 4,713,260 →
Application: 07/045,526 →
Large Signal Output Current Enhancement for a Differential Pair
Patent: 4,780,688 →
Application: 07/046,691 →
Structure for High Breakdown Pn Diode with Relatively High Surface Doping
Patent: 4,713,681 →
Application: 07/048,482 →
Bonding Technique to Join Two or More Silicon Wafers
Patent: 4,854,986 →
Application: 07/049,637 →
Performing Binary Multiplication Using Minimal Path Algorithm
Patent: 4,823,300 →
Application: 07/051,386 →
Multiple Layer, Tungsten/Titanium/Titanium Nitride Adhesion/Diffusion Barrier Layer Structure for Gold-Base Microcircuit Interconnection
Patent: 4,753,851 →
Application: 07/055,356 →
Self-Aligned Contact for Mos Processing
Patent: 4,795,718 →
Application: 07/057,398 →
Self-Aligned Contacts for Bipolar Process
Patent: 4,752,591 →
Application: 07/062,309 →
Dielectric Isolation Process Using Double Wafer Bonding
Patent: 4,851,078 →
Application: 07/067,838 →
Controlled Switching Cmos Output Buffer
Patent: 4,818,901 →
Application: 07/075,641 →
Technique for Elimination of Polysilicon Stringers in Direct Moat Field Oxide Structure
Patent: 4,908,683 →
Application: 07/084,556 →
Double Epitaxial Method of Fabricating Semiconductor Devices on Bonded Wafers
Patent: 4,897,362 →
Application: 07/092,975 →
Chip Carrier Soldering Pallet
Patent: 4,801,065 →
Application: 07/103,620 →
Cell Based Alu with Tree Structured Carry, Inverting Logic and Balanced Loading
Patent: 4,882,698 →
Application: 07/106,071 →
Conductivity-Modulated Fet with Improved Pinch Off-Ron Performance
Patent: 4,873,564 →
Application: 07/110,775 →
Operational Amplifier Having Low Dc Current Input Circuit
Patent: 4,855,625 →
Application: 07/118,251 →
Cell Based Adder with Tree Structured Carry, Inverting Logic and Balanced Loading
Patent: 5,047,974 →
Application: 07/124,807 →
High Voltage Ic Bipolar Transistors Operable to Bvcbo and Method of Fabrication
Patent: 4,808,547 →
Application: 07/130,521 →
Speed Enhancement for Multipliers Using Minimal Path Algorithm
Patent: 4,868,778 →
Application: 07/132,186 →
Method of Packaging a Non-Contact I/O Signal Transmission Integrated Circuit
Patent: 4,845,052 →
Application: 07/143,328 →
Ion Implanted Jfet with Self-Aligned Source and Drain
Patent: 4,912,053 →
Application: 07/151,184 →
Isolated Gate Mesfet and Method of Making and Trimming
Patent: 4,948,746 →
Application: 07/164,342 →
Self-Planarized Gold Interconnect Layer
Patent: 4,970,573 →
Application: 07/181,718 →
Method of Etching Silicon by Enhancing Silicon Etching Capability of Alkalli Hydroxide Through the Addition of Positive Valence Impurity Ions
Patent: 4,859,280 →
Application: 07/187,268 →
Method and Apparatus for Computing Square Roots of Binary Numbers
Patent: 4,949,296 →
Application: 07/195,265 →
Integrated Circuits Including Photo-Optical Devices and Pressure Transducers and Method of Fabrication
Patent: 4,916,497 →
Application: 07/195,273 →
Current Compensated Precharged Bus
Patent: 4,857,764 →
Application: 07/213,823 →
Technique for Forming Planarized Gate Structure
Patent: 4,818,725 →
Application: 07/224,320 →
Compensated Current Sensing Circuit
Patent: 4,820,968 →
Application: 07/224,636 →
Trench Gate Vcmos
Patent: 4,951,102 →
Application: 07/235,543 →
High Breakdown Active Device Structure with Low Series Resistance
Patent: 4,975,751 →
Application: 07/253,437 →
Fast Level Translator Circuit
Patent: 4,897,567 →
Application: 07/257,015 →
High Accuracy Current Source and High Accuracy Transconductance Stage
Patent: 4,879,520 →
Application: 07/263,189 →
Method for Forming Complementary Patterns in a Semiconductor Material While Using a Single Masking Step
Patent: 4,956,306 →
Application: 07/266,756 →
Fast Image Processing Accelerator for Real Time Image Processing Applications
Patent: 4,937,774 →
Application: 07/266,812 →
Transimpedance Focal Plane Processor
Patent: 4,893,088 →
Application: 07/271,656 →
High Accuracy, High Impedance Differential to Single-Ended Current Converter
Patent: 4,879,523 →
Application: 07/272,908 →
Dielectric Isolation for Soi Island Side Wall for Reducing Leakage Current
Patent: 5,034,789 →
Application: 07/274,176 →
Method of Fabrication of Isolated Islands for Complementary Bipolar Devices
Patent: 4,900,689 →
Application: 07/281,546 →
Method of Fabricating Back Diffused Bonded Oxide Substrates
Patent: 4,968,628 →
Application: 07/282,064 →
High Speed Low Input Current Voltage Follower Stage
Patent: 4,891,604 →
Application: 07/289,747 →
Memory with Cache Register Interface Structure
Patent: 4,888,741 →
Application: 07/289,748 →
Dielectric for Laser Trimming
Patent: 4,839,711 →
Application: 07/296,855 →
Method of Making Silicon-on-Insulator Islands
Patent: 4,897,366 →
Application: 07/298,148 →
Method of Making Cmos with Shallow Source and Drain Junctions
Patent: 4,945,070 →
Application: 07/301,073 →
Low Top Gate Resistance Jfet Structure
Patent: 4,876,579 →
Application: 07/301,835 →
Voltage Limiter Apparatus with Inherent Level Shifting Employing Mosfets
Patent: 4,945,262 →
Application: 07/301,926 →
High Voltage Mos Structure
Patent: 4,941,027 →
Application: 07/302,386 →
Method of Edge Doping Soi Islands
Patent: 5,053,345 →
Application: 07/306,356 →
Photocurrent Compensation Using Active Devices
Patent: 4,891,606 →
Application: 07/307,944 →
Ic Which Eliminates Support Bias Influence on Dielectrically Isolated Components
Patent: 4,923,820 →
Application: 07/311,812 →
Voltage Regulator Having Staggered Pole-Zero Compensation Network
Patent: 4,908,566 →
Application: 07/313,435 →
Vertical Contact Structure
Patent: 4,914,501 →
Application: 07/334,148 →
Forth Specific Language Microprocessor
Patent: 5,070,451 →
Application: 07/336,632 →
Back-Sampling Charge Redistribution Analog to Digital Converter
Patent: 4,982,194 →
Application: 07/340,705 →
Programmable Delay Circuit
Patent: 5,028,824 →
Application: 07/347,574 →
Analog-To-Digital Converter and Method of Use Vitilizin Charge Redistrebution
Patent: 5,014,055 →
Application: 07/356,084 →
Semiconductor Transmission Gate with Capacitance Compensation
Patent: 4,988,902 →
Application: 07/356,086 →
Unity-Gain Cmos/Sos Zero-Offset Buffer
Patent: 4,978,925 →
Application: 07/356,311 →
Thin Film Resistors and Method of Trimming
Patent: 4,929,923 →
Application: 07/357,898 →
Precise, High Speed Cmos Track (Sample)/Hold Circuits
Patent: 5,036,219 →
Application: 07/359,176 →
Full Adder Circuit with Improved Carry and Sum Logic Gates
Patent: 4,970,677 →
Application: 07/361,439 →
Bipolar Transistor with High Efficient Emitter
Patent: 5,028,973 →
Application: 07/367,788 →
High Speed, High Precision Operational Amplifier
Patent: 4,980,651 →
Application: 07/370,280 →
A Method of Making Dielectrically Isolated Intergrated Circuits Using Oxygen Implantation and Epitaxial Growth
Patent: 4,929,566 →
Application: 07/376,019 →
Method of Making Edge-Connected Integrated Circuit Structure
Patent: 5,081,063 →
Application: 07/382,388 →
Programmable Speed/Power Arrangement for Integrated Devices Having Logic Matrices
Patent: 4,968,900 →
Application: 07/387,534 →
Method for Forming Dielectrically Isolated Transistor
Patent: 4,923,826 →
Application: 07/388,416 →
Simplified Transistor Base Current Compensation Circuitry
Patent: 4,978,868 →
Application: 07/390,147 →
Predrive Circuit Having Level Sensing Control
Patent: 5,051,619 →
Application: 07/403,865 →
Method of Isolating a Top Gate of a Mesfet and the Resulting Device
Patent: 4,929,568 →
Application: 07/405,282 →
Radiation Hardened Complementary Transistor Ingrated Circuits
Patent: 5,021,359 →
Application: 07/416,419 →
Method of Making a Mos Transistor
Patent: 4,927,777 →
Application: 07/418,762 →
Dual Layer Surface Gate Jfet Having Enhanced Gate-Channel Breakdown Voltage
Patent: 5,008,719 →
Application: 07/424,917 →
A-B Buffer Circuit with Ttl Compatible Output Drive
Patent: 5,015,887 →
Application: 07/431,517 →
Method and Circuit Arrangement for Providing Programmable Hysteresis to a Differential Comparator
Patent: 5,039,888 →
Application: 07/436,247 →
Content Addressable Memory Device
Patent: 5,051,949 →
Application: 07/437,472 →
Automatic Esd Protection Device for Semiconductor Packages
Patent: 5,038,248 →
Application: 07/447,618 →
Scr Structure for Fast Turn-on Switching
Patent: 4,979,011 →
Application: 07/451,249 →
Cross-Point Switch
Patent: 5,060,192 →
Application: 07/457,504 →
Method of Fabricating Integrated Circuits Including Photo Optical Devices and Pressures Transducers.
Patent: 5,037,765 →
Application: 07/465,314 →
Trench-Resident Interconnect Structure
Patent: 5,070,388 →
Application: 07/467,590 →
Current Mirror Circuit with Cascoded Transistors
Patent: 5,248,932 →
Application: 07/474,172 →
Turn-Off Circuit for Gate Turn Off Scr
Patent: 5,030,862 →
Application: 07/474,417 →
Variable Length Shift Register
Patent: 5,084,839 →
Application: 07/475,007 →
Digital Signal Processing Address Sequencer
Patent: 5,265,225 →
Application: 07/482,803 →
Manufacturing Ultra-Thin Wafer Using a Handle Wafer
Patent: 5,034,343 →
Application: 07/490,316 →
Method of Forming a High Voltage Junction in a Dielectrically Isolated Island
Patent: 5,079,176 →
Application: 07/498,642 →
Reduced Contact Resistance on a Slic
Patent: 5,148,475 →
Application: 07/505,899 →
Low Distortion Sample and Hold Circuit
Patent: 5,015,877 →
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Ultra-Thin Circuit Fabrication by Controlled Wafer Debonding
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Application: 07/509,405 →
Digital Decimation Filter
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Adaptive Threshold Suppression of Impulse Noise
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Mesfet for Dielectrically Isolated Integrated Circuits
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Band-Gap Reference
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Trench Gate Vcmos Method of Manufcture
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An Isolated Gate Mesfet and Method of Making and Trimming
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Sin/Cos Generator Implementation
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Trench Conductor and Crossunder Architecture
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Back-Sampling Analog to Digital Converter
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Method of Making a High Breakdown Active Device Structure with Low Series Resistance
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Fast Turn-Off of Thyristor Structure
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Piso Electrostatic Discharge Protection Device
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Stacked Configuration for Integrated Circuit Devices
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Integrated Circuits Including Photo-Optical Devices and Pressure Transducers and Method of Fabrication
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Method of Making Silicon Mesfet for Dielectrically Isolated Integrated Circuits
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Power Mosfet
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Power Mosfet Transistor Circuit with Active Clamp
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Dual Layer Surface Gate Jfet Having Enhanced Gate-Channel Breakdown Voltage
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Method and Apparatus for Testing Lead Bonds and Detecting Failure
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Single Chip 2-D Convolver
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Direct Bonding of Copper to Aluminum Nitride Substrates
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Multiplexed Sigma-Delta a/D Converter
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Photolithographic Formation of Die-to-Package Airbridge in a Semiconductor Device
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A Dielectric Isolation for Soi Island Side Wall for Reducing Leakage Current
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Single Power Mosfet Ac Power Switch Employing Means for Preventing Conduction of Body Diode
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Converter Comparartor Cell with Improved Resolution
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Semiconductor Structure Within Di Islands Having Bottom Projection for Controlling Device Characteristics
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Method of Forming Self-Aligned Top Gate Channel Barrier Region in Ion-Implanted Jfet
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Level Shift Circuit with Common Mode Rejection
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Semiconductor Device with Improved Turn-Off Capability
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Power-On Reset Circuit
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Manufacturing Ultra-Thin Dielectrically Isolated Wafers
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Method of Isolating a Top Gate of a Mesfet and the Resulting Device
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Power Vdmosfet with Schottky on Lightly Doped Drain of Lateral Driver Fet
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A Cover with Through Terminals for a Hermetically Sealed Electronic Package
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Graded Collector for Inductive Loads
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Self-Aligned Channel Stop for Trench-Isolated Island
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Latching Comparator Employing Transfer Gates
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Method of Laser Trimming
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Voltage Divider and Use as Bias Network for Stacked Transistors
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Full Range Input/Output Comparator
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High Voltage Lateral Semiconductor Device
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Overvoltage Sensor with Hysteresis
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Low Offset Unity Gain Buffer Amplifier
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High Speed Differential Comparator
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Decimation Circuit Employing Multiple Memory Data Shifting Section and Multiple Arithmetic Logic Unit Section
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High Voltage Protection Using Scrs
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Method of Making Trench Conductor and Crossunder Architecture
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Buried Zener Diode Having Auxiliary Zener Junction Access Path
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Integrating a/D Converter with Means for Reducing Rollover Error
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Forth Specific Language Microprocessor
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Two Stage a/D Converter Utilizing Dual Multiplexed Converters with a Common Converter
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Thin, Dielectrically Isolated Island Resident Transistor Structure Having Low Collector Resistance
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Resistor Structure and Method of Fabrication
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Noncanonic Fully Systolic Lms Adaptive Architecture
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Fold and Decimate Filter Architecture
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Bimos Current Driver Circuit
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Analog-To-Digital Converter and Method of Fabrication
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Differential Voltage Follower
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Power Fet Having Reduced Threshold Voltage
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Print Band Cleaner
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Symmetric, High Speed, Voltage Switching Circuit Possessing Reverse Viltage Application Immunity
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Power Fet with Shielded Channels
Patent: 5,243,211 →
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Process for Forming Extremely Thin Edge-Connectable Integrated Circuit Structure
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High Speed Bipolar Digital Logic Gate Architecture
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Field Effect Transistor Controlled Thyristor Having Improved Turn-on Characteristics
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Flash Analog-to-Digital Converter Employing Least Significant Bit- Representative Comparative Reference Voltage
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Bias Current Modulation for Differentially Coupled Transistor Circuit
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Power Fet with Gate Segments Covering Drain Regions Disposed in a Hexagonal Pattern
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Semiconductor Devices and Methods of Assembly Thereof
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Method of Manufacturing a Multi-Layered I C Packaging Assembly
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Reduced Semiconductor Size Package
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Selective Recrystallization to Reduce P-Channel Transistor Leakage in Silicon-on-Sapphire Cmos Radiation Hardened Integrated Circuits
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Wafer Bonding Process Emplyoing Liquid Oxidant
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Hermetic Ic Package Moisture Tester
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Telephone Subscriber Line Circuit, Components and Methods
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Method and Device in Which Bottoming of a Well in a Dielectrically Isolated Island Is Assured
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Electrically Programmable Memory Cell
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Semiconductor Device with Improved Turn-Off Capability
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Laser Trimmed Integrated Circuit
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Method of Forming Island with Polysilicon-Filled Trench Isolation
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Soi Cmos Device Having Differentially Doped Body Extension for Providing Improved Backside Leakage Channel Stop
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Power Driver Circuit
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Integration of High Voltage Lateral Mos Devices in Low Voltage Cmos Architecture Using Cmos-Compatible Process Steps
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Soi Wafer with Sige
Patent: 5,218,213 →
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Method of Fabricating Soi Water with Sige as an Etchback Film in a Besoi Process
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Precision Voltage Reference Circuit
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Seu-Immune Latch for Gate Array, Standard Cell, and Other Asic Applications
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Reduced Temperature Suppression of Volatilization of Photoexcited Halogen Reaction Products from Surface of Silicon Wafer
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Gas Phase Chemical Reduction of Metallic Branding Layer of Electronic Circuit Package for Deposition of Branding Ink
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Trench Conductor and Crossunder Architecture
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Bicmos Devices
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Breakdown Diode Structure
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Bonded Wafer Processing
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Formation of Dual Polarity Source/Drain Extensions in Lateral Complementary Channel Mos Architectures
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Process for Forming Twin Well Cmos Integrated Circuits
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Quadrature Filter with Real Conversion
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Decimation Filter and Method
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Digital Down Converter and Method
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Current Driver Having Voltage Transition Failure-Based Short Circuit Protecton Circuit
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Sine/Cosine Generator and Method
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Semiconductor Rom Device and Method
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Method for Forming Recessed Oxide Isolation Containing Deep and Shallow Trenches
Patent: 5,382,541 →
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Circuit for Providing a Current Proportional to Absolute Temperature
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Comparator Amplifier
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Application: 07/936,596 →
Stress Relief Technique of Removing Oxide from Surface of Trench- Patterned Semiconductor-on-Insulator Structure
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Bonded Wafer Processing with Metal Silicidation
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Inductive Load Dump Circuit
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Decimating Filter
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Application: 07/945,674 →
Reduction of Bipolar Gain and Improvement in Snap-Back Sustaining Voltage in Soi Field Effect Transistor
Patent: 5,315,144 →
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Non-Linear Operational Transconductance Amplifier
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Resource Access Security System for Controlling Access to Resources of a Data Processing System
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Device and Method for Improving Current Carrying Capability in a Semiconductor Device
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Plural - Bit Recoding Multiplier
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Amplifier System for Low Level Sensor Signal
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Amplifier with High Common Mode Rejection
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Static Electricity Dispersant
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Electrostatic Discharge Protection
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Improved Sigma-Delta Type Analog-Digital Converter and Method
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Decoupling Tool Mechanism for Electrical Connectors
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Spiral Edge Passivation Structure for Semiconductor Devices
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High Speed Differential Comparator
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Circuit and Method for Extending the Safe Operating Area of a Bjt
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Bonded Wafer Process Incorporating Diamond Insulator
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Curing of a Tungsten Filament in an Ion Implanter
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Semi-Conductor Chip Packaging Method and Semi-Conductor Chip Having Interdigitated Gate Runners with Gate Bonding Pads
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Fast Turn on Switch Circuit with Parallel Mos Controlled Thyristor and Silicon Controlled Rectifier
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An Integrated Circuit with Improved Reverse Bias Breakdown
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Method of Making Intergrated Circuit Structure with Narrow Line Widths
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Biasing of Island-Surrounding Material to Suppress Reduction of Breakdown Voltage Due to Field Plate Acting on Buried Layer/Island Junction Between High and Low Impurity Concentration Regions
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Integrated Circuit Thermal Sensor
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Voltage Divider and Use as Bias Network for Stacked Transistors
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Process for Forming Twin Well Cmos Integrated Circuits
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Differential Amplifier with Hysteresis
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Low Voltage Rf Amplifier and Mixer with Single Bias Block and Method
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Fast Charging Mos Capacitor Structure for High Magnitude Voltage of Either Positive or Negative Polarity
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Method and Device in Which Bottoming of a Well in a Dielectrically Isolated Island Is Assured
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Self-Aligned Channel Stop for Trench-Isolated Island
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Method for Interactively Tailoring Topography of Integrated Circuit Layout in Accordance with Electromigration Model-Based Minimum Width Metal and Contact/via Rules
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Semiconductor Device with a Foil Sealed Lid
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Sub-Micron Bonded Soi by Trench Planarization
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Fill and Etchback Process Using Dual Photoresist Sacrificial Layer and Two-Step Etching Process for Planarizing Oxide-Filled Shallow Trench Structure
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Methods for Forming a Transistor Having an Emitter with Enhanced Efficiency
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Die Separation Method for Silicon on Diamond Circuit Structures
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High Frequency Analog Transistors, Method of Fabrication and Circuit Implementation
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Resistance-Measurement Based Arrangement for Monitoring Integrity of Travel Path Ground Link in Electronic Components Handling Apparatus
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Method of Manufacture of Multi-Cell Integrated Circuit Architecture
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Wafer Bonding Using Trapped Oxidizing Vapor
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Mesh Geometry for Mos-Gated Semiconductor Devices
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Selective Recrystallization to Reduce P-Channel Transistor Leakage in Silicon-on-Sapphire Cmos Radiation Hardened Integrated Circuits
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Apparatus and Method for Increasing Breakdown Voltage Ruggedness in Semiconductor Devices
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Package for Parallel Subelement Semiconductor Devices
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Fail-Safe Mos Shutdown Circuitry
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Voltage Independent Symmetrical Current Source with Cross-Coupled Transistors
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Trench Resistor Architecture
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Method for Providing a Silicon and Diamond Substrate Having a Carbon to Silicon Transition Layer and Apparatus Thereof
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Method of Making an Improved Graded Collector for Inductive Loads
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Differential Voltage Monitor Using a Bridge Circuit with Resistors on and Off an Integrated Circuit
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Plasma Cleaning Method for Improved Ink Brand Permanency on Ic Packages with Metallic Parts
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Esd Protection Using Scr Clmaping
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Current Mirror with Saturation Limiting
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Current Rise and Fall Time Limited Voltage Follower
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Reverse Current Flow Prevention in a Diffused Resistor
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Semiconductor Accelerometer and Method of Its Manufacture
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Hermetic Package for a High Power Semiconductor Device
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Device for Isolating Parallel Sub-Elements with Reverse Conducting Diode Regions
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Integration of High Voltage Lateral Mos Devices in Low Voltage Cmos Architecture Using Cmos-Compatible Process Steps
Patent: 5,541,435 →
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Digital Baseband to If Conversion in Cellular Base Stations
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Method of Doping a Jfet Region in a Mos-Gated Semiconductor Device
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Silicon on Diamond Circuit Structure
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High Voltage Protection Using Scrs
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Process for Manufacturing a Multi-Port Adhesive Dispensing Tool
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Current Follower with Zero Input Impedance
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Impedance Setting Circuit for a Slic
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Ground Key Detector for a Slic
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Distortionless X-Ray Inspection
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Integrated Ringer Relay Circuit and Method
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High Speed a/D Converter and Slew Controlled Pulse Detector
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Graphical Display Discriminant Factor Indicator for Anomaly Identification in Semiconductor Manufacture Batch Process
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Semiconductor Device with Improved Turn-Off Capability
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Semi-Conductor Chip Having Interdigitated Gate Runners with Gate Bonding Pads
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Method of Making Contact Regions for Narrow Trenches in Semiconductor Devices
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Analog-To-Digital Converter and Reference Voltage Circuitry
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Bonded Wafer Processing
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Trench Isolation Stress Relief
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High Speed Comparator
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Video Scaling Method and Device
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Half-Band Filter and Method
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Voltage Clamp Circuit and Method
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Wafer Bonding for Power Devices
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Method for Formation of a Well in a Dielectrically Isolated Island
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Programmable Element in Barrier Metal Device
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Structure and Tailoring Effective Resistivity of a Sipos Layer by Patterning and Control of Dopant Introduction
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Sigma-Delta Analog to Digital Converter with Three Point Calibration Apparatus and Method
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Low Inductance Conductor Topography for Mosfet Circuit
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Method for Making Ohmic Contact to Lightly Doped Islands from a Silicide Buried Layer and Applications
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Method for Forming Relessed Oxide Isolation Containing Deep and Shallow Trenches
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Differential Longitudinal Amplifier for a Subscriber Line Interface Circuit
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Multiport Memory and Method
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Multiport Memory and Method
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Bonded Wafer Processing with Metal Silicidation
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Methoe of Forming Mos-Gated Semiconductor Devices Having Mesh Geometry Pattern
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Switch Controller and Method
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Comfet Switch and Method
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Current Mode Ring Trip Detector
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Double Duty Capacitor Circuit and Method
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Circuit and Method for Loopback Test and on-Hook Transmission Integrated in a Telephone Subscriber Line Interface Circuit
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Filter with Reduced Element Ratings and Method
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Method and Circuit for Failsafe Switch-Hook Detection During Fault in a Telephone System
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Configuration Independent Auto-Biasing of Bipolar Transistor
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High Voltage, Junction Isolation Semiconductor Device Haivng Dual Conductivity Tape Buried Regions and Its Process of Manufacture
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Simulation of Noise Behavior of Non-Linear Circuit
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Direct Etch for Thin Film Resistor Using a Hard Mask
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Analog-To-Digital Converter
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Method of Scaling the Outputs of a Binary Counter
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Multiple Use Timer and Method for Pulse Width Generation, Echo Failure Detection, and Receive Pulse Width Measurement
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Crc Generation and Detection Method
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Modification of Timing in an Emulator Circuit and Method
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Zero Phase Error Switched-Capacitor Phase Locked Loop Filter
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Process for Doping Two Levels of a Double Poly Bipolar Transistor After Formation of Second Poly Layer
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Digital Component Testing Apparatus and Method
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Method of Forming Dummy Island Capacitor
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Bonded Wafer Processing with Oxidative Bonding
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Methods of Mass Production of Semiconductor Devices
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Multi-Channel Sigma-Delta a/D Converters with Improved Throughput
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Rate Change Filter and Method
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Bimos Driver Circuit and Method
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Bonded Wafer and Method of Fabrication Thereof
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Sense Amplifier for a Multiport Memory and Method
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Rom Cell for a Multiport Memory and Method
Patent: 5,544,095 →
Application: 08/450,879 →
Method of Forming P-Type Islands Over P-Type Buried Layer
Patent: 5,633,180 →
Application: 08/456,727 →
Phase Generator
Patent: 5,570,392 →
Application: 08/456,859 →
Fixed Coefficient High Decimation Filter
Patent: 5,617,344 →
Application: 08/457,234 →
Method of Manufacturing a Semiconductor Accelerometer
Patent: 5,656,512 →
Application: 08/457,643 →
Integrated Circuit Method for and Structure with Narrow Line Widths
Patent: 5,773,891 →
Application: 08/460,993 →
Integrated Circuit with Coaxial Isolation and Method
Patent: 5,814,889 →
Application: 08/461,037 →
Surface Mountable Integrated Circuit with Conductive Vias
Patent: 5,608,264 →
Application: 08/461,643 →
Method of Bonding Wafers Having Vias Including Conductive Material
Patent: 5,646,067 →
Application: 08/461,951 →
Method of Fabrication of Surface Mountable Integrated Circuits
Patent: 5,618,752 →
Application: 08/462,171 →
A True/Complementer for a Half-Band Filter
Patent: 5,574,671 →
Application: 08/462,684 →
High Frequency Analog Transistors, Method of Fabrication and Circuit Implementation
Patent: 5,807,780 →
Application: 08/462,851 →
Hermetic Package for a High Power Semiconductor Device
Patent: 5,577,656 →
Application: 08/462,856 →
System for Interconnecting Stacked Integrated Circuits
Patent: 5,682,062 →
Application: 08/462,876 →
Integrated Circuit with Edge Connections and Method
Patent: 5,668,409 →
Application: 08/463,388 →
Method of Increasing Maximum Terminal Voltage of a Semiconductor Device
Patent: 5,665,634 →
Application: 08/463,560 →
Trench Isolation Stress Relief
Patent: 5,683,075 →
Application: 08/465,246 →
Diamond Insulator Devices and Method of Fabrication
Patent: 5,683,939 →
Application: 08/471,759 →
High Efficiency Quasi-Vertical Dmos in Cmos or Bicmos Process
Patent: 5,777,362 →
Application: 08/474,559 →
Method of Making an Integration of High Voltage Lateral Mos Devices in Low Vltage Cmos-Compatible Process Steps
Patent: 5,622,878 →
Application: 08/474,647 →
Semiconductor Package and Method with Vertically Extended Electrode Leads
Patent: 5,517,058 →
Application: 08/476,679 →
Digital Down Converter and Method
Patent: 5,757,794 →
Application: 08/478,682 →
Formatter
Patent: 5,633,815 →
Application: 08/478,683 →
Defect Control in Formation of Dielectrically Isolated Semiconductor Device Regions
Patent: 5,750,432 →
Application: 08/481,115 →
Local Oxidation Process for High Field Threshold Applications
Patent: 5,580,816 →
Application: 08/481,116 →
High Efficiency Power Mos Switch
Patent: 5,689,129 →
Application: 08/483,691 →
Pilot Transistor for Quasi-Vertical Dmos Device
Patent: 5,684,305 →
Application: 08/483,692 →
Battery Operated Inverter Circuit for Capacitive Loads Such as Electroluminescent Lamps
Patent: 5,557,175 →
Application: 08/490,016 →
Efficient Battery Operated Inverter Circuit for Capacitive Loads Such as Electroluminescent Lamps
Patent: 5,525,869 →
Application: 08/490,566 →
Electroluminescent Lamp Driver System
Patent: 5,539,707 →
Application: 08/490,952 →
Sign Bit Integrator and Method
Patent: 5,617,473 →
Application: 08/493,454 →
Level Shifter with Improved Rejection of Voltage Variations
Patent: 5,627,489 →
Application: 08/493,824 →
Offset Adjustment for Fully Differential Amplifiers
Patent: 5,736,885 →
Application: 08/494,395 →
Digital Decoder and Method for Decoding Composite Video Signals
Patent: 5,621,477 →
Application: 08/496,868 →
Multistandard Decoder for Video Signals and Video Signal Decoding Method
Patent: 5,621,478 →
Application: 08/497,008 →
Temperature Insensitive Filter Tuning Network and Method
Patent: 5,572,161 →
Application: 08/497,045 →
Scr Inductor Transient Clamp
Patent: 5,546,038 →
Application: 08/497,124 →
Sample Rate Converter and Sample Rate Conversion Method
Patent: 5,619,270 →
Application: 08/497,181 →
Semi-Insulating Wafer
Patent: 5,773,151 →
Application: 08/497,404 →
Method of Making Non-Uniformly Nitrided Gate Oxide
Patent: 5,650,344 →
Application: 08/503,048 →
Fast Recovery Temperature Compensated Reference Source
Patent: 5,621,307 →
Application: 08/505,671 →
Automatic Fault Monitoring System and Motor Control System Incorporating Same
Patent: 5,642,247 →
Application: 08/505,695 →
Inverted Bjt Current Sources/Sinks in Rf Circuits and Methods
Patent: 5,654,662 →
Application: 08/506,978 →
Device and Method for Enhancing Thermal and High Frequency Performance of Integrated Circuit Packages
Patent: 5,581,444 →
Application: 08/507,192 →
Packet Header Generation and Detection Circuitry
Patent: 5,712,870 →
Application: 08/509,462 →
A Method of Estimating Signal Quality in a Dpsk Demodulator
Patent: 5,732,105 →
Application: 08/509,586 →
Short Burst Acquisition Circuit for Direct Sequence Spread Spectrum Links
Patent: 5,883,921 →
Application: 08/509,587 →
Fast Acquisition Bit Timing Loop Method and Apparatus
Patent: 5,654,991 →
Application: 08/509,588 →
A/D Reference Level Adjustment Circuit to Maintain Optimum Dynamic Range at the A/D
Patent: 5,675,339 →
Application: 08/509,589 →
Short Burst Direct Acquisition Direct Sequence Spread Spectrum Receiver
Patent: 5,694,417 →
Application: 08/509,590 →
Arrangement and Method for Improving Room-Temperature Testability of Cmos Integrated Circuits Optimized for Cryogenic Temperature Operation
Patent: 5,696,452 →
Application: 08/512,323 →
Differential Transimpedance Amplifier
Patent: 5,606,288 →
Application: 08/512,405 →
Wide Common Mode Range Comparator and Method
Patent: 5,614,852 →
Application: 08/512,417 →
Class D Amplifier and Method
Patent: 5,672,998 →
Application: 08/512,763 →
Integrated Circuit with Diamond Insulator
Patent: 5,650,639 →
Application: 08/513,950 →
Statistically Based Current Generator Circuit
Patent: 5,701,097 →
Application: 08/515,435 →
Interrupter Circuit with Mcts and Pulse Resonant Commutation for Rapidly Switching Off Kilo-Amp Ac Load Currents
Patent: 5,640,300 →
Application: 08/521,813 →
Method of Manufacturing a Programmable Hybrid Balance Network
Patent: 5,610,093 →
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Device and Method for Improving Corrosion Resistance and Etch Tool Integrity in Dry Metal Etching
Patent: 5,830,279 →
Application: 08/536,257 →
Sampled Data-Biasing of Continuous Time Integrated Circuit
Patent: 5,621,355 →
Application: 08/537,051 →
Method of Making Jfet Structures for Semiconductor Devices with Complementary Bipolar Transistors
Patent: 5,652,153 →
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Testing Circuit and Method for a Codec Hybrid Balance Network
Patent: 5,717,736 →
Application: 08/552,379 →
Magnetic Boats
Patent: 5,669,599 →
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Improved Discrete Programming Methodology and Circuit for an Active Transconductance-C Filter
Patent: 5,666,083 →
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Apparatus for Controlling the Reset of a Bus Connected Transceiver
Patent: 5,610,792 →
Application: 08/562,609 →
Two Stage Current Mirror
Patent: 5,631,599 →
Application: 08/571,693 →
Silicon-Glass Bonded Wafers
Patent: 5,729,038 →
Application: 08/573,099 →
Bonded Wafer Processing
Patent: 5,728,624 →
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Common Mode Stabilizing Circuit and Method
Patent: 5,668,468 →
Application: 08/584,366 →
Method and Apparatus for Radiation Hardened Isolation
Patent: 5,670,413 →
Application: 08/586,556 →
Metal Oxide Semiconductor Controlled Thyristor with an on-Field Effect Transistor in a Trench
Patent: 5,777,346 →
Application: 08/586,613 →
Composition, and Method for Using Same, for Etching Metallic Alloys from a Substrate
Patent: 5,587,103 →
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Method for Providing a Silicon and Diamond Substrate Having a Carbon to Silicon Transistion Layer and Apparatus Thereof
Patent: 5,782,975 →
Application: 08/587,953 →
Differential Interpolating Switched Capacitor Filter and Method
Patent: 5,680,072 →
Application: 08/590,940 →
Electrostatic Discharge Protection Device
Patent: 5,883,414 →
Application: 08/596,079 →
Interpolating Digital to Analog Converter Architecture for Improved Spurious Signal Suppression
Patent: 5,798,724 →
Application: 08/601,401 →
Method to Improve the Peak-Current Limit in a Slope-Compensated, Current-Mode Dc/Dc Converter, and Circuit Therefor
Patent: 5,717,322 →
Application: 08/602,287 →
Phase Meter and Method of Providing a Voltage Indicative of a Phase Difference
Patent: 5,831,423 →
Application: 08/608,728 →
Digitally Programmable Differential Attenuator with Tracking Common Mode Reference
Patent: 5,742,204 →
Application: 08/608,812 →
Integration of High Voltage Lateral Mos Devices in Low Voltage Cmos Architecture Using Cmos-Compatible Process Steps
Patent: 5,650,658 →
Application: 08/612,695 →
Circuit for Driving an Electroluminescent Lamp
Patent: 5,677,599 →
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Integrated Circuit with Power Monitor
Patent: 5,682,111 →
Application: 08/630,874 →
Asymmetric Snubber Resistor
Patent: 5,880,513 →
Application: 08/634,371 →
Trench Mos Gate Device
Patent: 5,770,878 →
Application: 08/636,904 →
Integrated Circuit with an Improved Inductor Structure and Method of Fabrication
Patent: 5,717,243 →
Application: 08/637,132 →
Carrier Buffer Having Current-Controlled Tracking Filter for Spurious Signal Suppression
Patent: 5,736,903 →
Application: 08/637,140 →
Method of Making a Reference Current Generator
Patent: 5,686,822 →
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Planarization Method by Use of Particle Dispersion and Subsequent Thermal Flow
Patent: 5,837,603 →
Application: 08/643,295 →
Analog-To-Digital Converter and Output Driver
Patent: 5,659,261 →
Application: 08/645,139 →
Semiconductor Device with Doped Semiconductor and Dielectric Trench Sidewall Layers
Patent: 5,856,700 →
Application: 08/646,471 →
Integrated Circuit with an Air Bridge Having a Lid
Patent: 5,825,092 →
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Method and Circuit for Preventing Forward Bias of a Parasitic Diode in an Integrated Circuit
Patent: 5,675,281 →
Application: 08/652,933 →
Process for Forming a Self-Aligned Raised Source/Drain Mos Device and Device Therefrom
Patent: 5,804,846 →
Application: 08/654,393 →
Bridge Control Circuit and Method
Patent: 5,870,266 →
Application: 08/656,987 →
Method for Fabricating a Power Device
Patent: 5,913,130 →
Application: 08/662,118 →
Radiation Hardened Dielectric for Eeprom
Patent: 5,808,353 →
Application: 08/666,258 →
Clock-Controlled Precision Monostable Circuit
Patent: 5,920,219 →
Application: 08/669,066 →
Double Diffused Mos Device and Method
Patent: 5,817,564 →
Application: 08/671,157 →
Integrated Circuit Containing Devices Dielectrically Isolated and Junction Isolated from a Substrate
Patent: 5,841,169 →
Application: 08/671,243 →
Silent Start Class D Amplifier
Patent: 5,805,020 →
Application: 08/671,453 →
Charge-Based Frequency Locked Loop and Method
Patent: 5,841,324 →
Application: 08/671,781 →
High Voltage Protection Circuits
Patent: 5,663,860 →
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Method of Making High Voltage, Junction Isolation Semiconductor Device Having Dual Conductivity Type Buried Regions
Patent: 5,837,553 →
Application: 08/683,599 →
Electrically Variable R/C Network and Method
Patent: 5,767,757 →
Application: 08/687,995 →
Lid Wafer Bond Packaging and Micromachining
Patent: 5,798,557 →
Application: 08/705,536 →
P-Collector H.V. Pmos Switch Vt Adjusted Source/Drain
Patent: 5,770,880 →
Application: 08/707,271 →
Two Trim Current Source and Method for a Digital-to-Analog Converter
Patent: 5,923,209 →
Application: 08/707,380 →
Method of Forming Power Semiconductor Devices with Controllable Integrated Buffer
Patent: 5,872,028 →
Application: 08/708,712 →
Bonded Wafer
Patent: 5,744,852 →
Application: 08/710,694 →
Integrated Circuit Analog-to-Digital Converter and Associated Calibration Method and Apparatus
Patent: 5,771,012 →
Application: 08/712,027 →
Low Distortion Feedback Ic Amplifier and Method
Patent: 5,789,982 →
Application: 08/712,562 →
Digital- to- Analog Converter Having Enhanced Current Steering and Associated Method
Patent: 5,790,060 →
Application: 08/714,019 →
Wide Common Mode Range Comparator and Method
Patent: 5,789,949 →
Application: 08/719,873 →
Switching Amplifier Closed Loop Dual Comparator Modulation Technique
Patent: 5,767,740 →
Application: 08/722,354 →
Gain Control Circuit and Method
Patent: 5,812,029 →
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Integrated Circuit Having Enhanced Transient Voltage Protection and Associated Methods
Patent: 5,708,549 →
Application: 08/726,183 →
Surface Mount Die by Handle Replacement
Patent: 5,807,783 →
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Late Process Method for Trench Isolation
Patent: 5,872,044 →
Application: 08/733,368 →
Reconfigurable Filter System
Patent: 5,719,326 →
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Capacitor Structure in a Bonded Wafer and Method of Fabrication
Patent: 5,841,182 →
Application: 08/741,639 →
Late Process Method and Apparatus for Trench Isolation
Patent: 5,920,108 →
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Method for Cleaning Semiconductor Wafers to Improve Dice to Substrate Solderability
Patent: 5,833,758 →
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Plsma Cleaning Method for Improved Ink Brand Permanency on Ic Packages
Patent: 5,882,423 →
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Deep Trench Etch on Bonded Silicon Wafer
Patent: 5,914,280 →
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Process for Doping Two Levels of a Double Poly Bipolar Transistor After Formation of Second Poly Layer
Patent: 5,776,814 →
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Process for Doping Two Levels of a Double Poly Bipolar Transistor After Formation of Second Poly Layer
Patent: 5,686,322 →
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Complementary Mutliplexer with Low Disabled-Output Capacitance, and Method
Patent: 5,923,207 →
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Re-Sampling Circuit and Modulator Using Same
Patent: 5,764,113 →
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Bonded Wafer Processing
Patent: 5,780,311 →
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High Frequency Analog Transistors, Method of Fabrication and Circuit Implementation
Patent: 5,892,264 →
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Pivot Sample Block Cross-Section Tool
Patent: 5,830,048 →
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Dc-To-Dc Converter Having Enhanced Control Features and Associated Methods
Patent: 5,793,193 →
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Dc-To-Dc Converter Having Fast Over-Current Detection and Associated Methods
Patent: 5,821,740 →
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Dc-To-Dc Converter Having Charge Pump and Associated Methods
Patent: 5,808,883 →
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Ohmic Contact to Lightly Doped Islands from a Conductive Rapid Diffusion Buried Layer
Patent: 5,895,953 →
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Method of Making Mos-Gated Semiconductor Devices
Patent: 5,877,044 →
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Bonded Wafer Processing
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Integrated Circuit Chip Structure for Improved Packaging
Patent: 5,900,643 →
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Single Ended to Differential Converter and 50% Duty Cycle Signal Generator and Method
Patent: 5,896,053 →
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Temperature Insensitive Bandgap Voltage Generator Tracking Power Supply Variations
Patent: 5,856,742 →
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Non-Uniformly Nitrided Gate Oxide and Method
Patent: 5,808,348 →
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Self-Aligned Power Field Effect Transistor in Silicon Carbide
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Bipolar Semiconductor Power Controlling Devices with Heterojunction
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Method and Apparatus for Calibrating Integrated Circuit Analog-to-Digital Converters
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Processor Controlled Analog-to-Digital Converter Circuit
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Multilayer Microtip Probe and Method
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Comparator with Small Signal Suppression Circuitry
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Frequency Dependent Resistive Element
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Method Fo Fabricating Bicmos Devices
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Network for Improving Electro-Magnetice Interference Response
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Lid Wafer Bond Packaging and Micromachining
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Circuit and Method for Protecting from Overcurrent Conditions and Detecting an Open Electrical Load
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Related Assignments (9)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. Jan 14, 1981
From: MORCOM WILLIAM R.; FRIEDMAN GLENN M.
To: HARRIS CORPORATION, A CORP. OF DE
Reel/Frame 003850/0012 →
Assignment of Assignors Interest. Feb 5, 1981
From: PATTERSON RAYMOND B. III
To: HARRIS CORPORATION, A CORP. OF DEL.
Reel/Frame 003865/0841 →
Assignment of Assignors Interest. Feb 5, 1981
From: COHEN PAUL B.; YOUNG WILLIAM R.; EDWARDS W. DALE
To: HARRIS CORPORATION, A CORP. OF DEL.
Reel/Frame 003865/0839 →
Assignment of Assignors Interest. Mar 1, 1982
From: YOUNG, WILLIAM R.
To: HARRIS CORPORATION, A CORP. OF DE.
Reel/Frame 003982/0382 →
Assignment of Assignors Interest. Oct 30, 1991
From: RIEMER, DAVID W.
To: HARRIS CORPORATION
Reel/Frame 005958/0341 →
Assignment of Assignors Interest. Dec 17, 1991
From: KING, KEN R.; COTREAU, GERLAD M.
To: HARRIS CORPORATION A CORP. OF DELAWARE
Reel/Frame 005970/0561 →
Security Interest Nov 8, 1999
From: INTERSIL CORPORATION
To: CREDIT SUISSE FIRST BOSTON, AS COLLATERAL AGENT
Reel/Frame 010351/0410 →
Security Agreement May 5, 2010
From: INTERSIL CORPORATION; TECHWELL, INC.; INTERSIL COMMUNICATIONS, INC.; QUELLAN, INC.
To: MORGAN STANLEY & CO. INCORPORATED
Reel/Frame 024390/0608 →
Release of Security Interest May 26, 2010
From: CREDIT SUISSE FIRST BOSTON
To: INTERSIL CORPORATION
Reel/Frame 024445/0049 →