IP Library › Assignment 010579/0570
Patent Assignment
Reel/Frame 010579/0570

Assignment of Assignor's Interest

Recorded: 2000-01-24 Pages: 26
Assignor
UNITED SEMICONDUCTOR CORP.
Executed: 1999-12-30
Assignee
UNITED MICROELECTRONICS CORP.
SCIENCE-BASED INDUSTRIAL PARK, NO. 3, LI-HSIN RD. 2, HSINCHU, R.O.C, TAIWAN
Covered Properties (240)
Method for Fabricating Flash Memory Cells
Patent: 5,899,718 →
Application: 08/859,259 →
Method of Forming Fluorosilicate Glass (Fsg) Layers with Moisture-Resistant Capability
Patent: 6,284,677 →
Application: 08/868,752 →
Sub-Micron Mosfet
Patent: 5,899,719 →
Application: 08/888,714 →
Shallow Trench Isolation for Semiconductor Devices
Patent: 6,069,058 →
Application: 08/924,432 →
Method of Reducing Fringe Capacitance
Patent: 5,891,783 →
Application: 08/927,323 →
Method for Manufacturing Electrostatic Discharge Protection Device
Patent: 5,937,298 →
Application: 08/957,811 →
Test Connecting Device Including Testkey and Probe Card for Use in the Testing of Integrated Circuits
Patent: 5,949,240 →
Application: 08/959,520 →
Flash Memory Cell Structure Having a High Gate-Coupling Coefficient and a Select Gate
Patent: 5,852,313 →
Application: 08/967,940 →
Techniques for Reduced Dishing in Chemical Mechanical Polishing
Patent: 5,968,842 →
Application: 08/975,487 →
Flash Eeprom Device
Patent: 5,960,285 →
Application: 08/975,490 →
Dram Process with a Multilayer Stack Structure
Patent: 5,966,600 →
Application: 08/975,496 →
Method for Manufacturing a Comb-Shaped Lower Electrode for a Dram Capacitor
Patent: 5,840,606 →
Application: 08/977,539 →
Method and Controlling System for Preventing the Scratching of Wafer Backs by the Fetch Arm of a Stepper Machine
Patent: 6,097,992 →
Application: 08/991,187 →
Method for Forming Etox Cell Using Self-Aligned Source Etching Process
Patent: 6,096,624 →
Application: 08/992,884 →
Method of Fabricating Electrostatic Discharge Protection Device
Patent: 5,960,288 →
Application: 08/997,874 →
Split-Gate Flash Memory Cell Structure
Patent: 5,907,172 →
Application: 08/998,312 →
Method of Manufacturing a Split-Gate Flash Memory Cell
Patent: 5,872,036 →
Application: 08/998,331 →
Method of Manufacturing a Flash Memory Cell Having a Tunnel Oxide with a Long Narrow Top Profile
Patent: 5,972,752 →
Application: 08/998,725 →
Improved Method of Etching
Patent: 6,143,665 →
Application: 08/998,769 →
Flash Memory Cell Structure Having Electrically Isolated Stacked Gate
Patent: 5,932,910 →
Application: 08/998,772 →
A Process of Fabricating an Antifuse Structure
Patent: 5,915,171 →
Application: 09/000,962 →
Method for Improving Differential Etching Rate of a Metallic Layer
Patent: 6,033,588 →
Application: 09/000,966 →
Method for Preventing the Formation of Recesses in Borophosphosilicate Glass
Patent: 6,165,694 →
Application: 09/023,235 →
Method of Fabricating Capacitor
Patent: 6,037,234 →
Application: 09/023,879 →
Method of Fabricating Flash Memory Cell
Patent: 5,994,185 →
Application: 09/024,163 →
Flash Memory Cell
Patent: 6,157,057 →
Application: 09/024,782 →
Manufacturing Method for a Thin Film with an Anti-Reflection Rough Surface
Patent: 6,093,646 →
Application: 09/033,113 →
Method of Fabricating a Split Gate Flash Memory Device
Patent: 6,008,089 →
Application: 09/033,376 →
Method of Fabricating Shallow Trench Isolation
Patent: 5,981,402 →
Application: 09/040,912 →
Method of Inspecting a Defect on a Translucid Film
Patent: 5,907,397 →
Application: 09/045,325 →
Method of Forming a Self-Aligned Contact in Semiconductor Fabrications
Patent: 5,989,987 →
Application: 09/046,059 →
Method of Fabricating Split-Gate Flash Memory
Patent: 5,856,224 →
Application: 09/046,061 →
Method of Nitride-Sealed Oxide-Buffered Local Oxidation of Silicon
Patent: 5,970,364 →
Application: 09/048,697 →
Method to Grow Self-Aligned Silicon on a Poly-Gate, Source and Drain Region
Patent: 5,998,286 →
Application: 09/048,924 →
Method for Manufacturing Dram Capacitor
Patent: 6,087,218 →
Application: 09/054,836 →
Method of Fabricating Storage Capacitor for Dynamic Random-Access Memory
Patent: 6,140,180 →
Application: 09/054,837 →
Process for Fabricating Bottom Electrode of Capacitor
Patent: 5,933,728 →
Application: 09/054,838 →
Method for Manufacturing Dram Capacitor Incorporating Liquid Phase Deposition
Patent: 6,060,366 →
Application: 09/058,579 →
Method of Forming Capacitors
Patent: 6,060,367 →
Application: 09/059,686 →
Method for Manufacturing Capacitor's Lower Electrode
Patent: 6,080,633 →
Application: 09/061,658 →
Etching Machine Having Lower Electrode Bias Voltage Source
Patent: 6,106,660 →
Application: 09/062,116 →
Method for Forming Metallic Layer Using Inspected Mask
Patent: 6,143,652 →
Application: 09/063,672 →
Method of Fabricating Dual Cylindrical Capacitor
Patent: 5,998,259 →
Application: 09/066,196 →
Method of Planarizing Dielectric Layer
Patent: 6,277,754 →
Application: 09/067,548 →
Method of Fabricating Stack Capacitor
Patent: 5,981,337 →
Application: 09/070,374 →
Method of Manufacturing Self-Aligned Silicide
Patent: 6,150,264 →
Application: 09/075,420 →
Method of Fabricating Split-Gate Source Side Injection Flash Memory Array
Patent: 6,025,229 →
Application: 09/076,672 →
Fabricating Method of Non-Volatile Flash Memory Device
Patent: 6,096,605 →
Application: 09/076,676 →
Method of Fabricating Bit Line
Patent: 6,051,469 →
Application: 09/082,660 →
Method of Fabricating a Static Random Access Memory
Patent: 5,943,566 →
Application: 09/084,766 →
Method of Fabricating a Capacitor Over a Bit Line of a Dram
Patent: 6,001,686 →
Application: 09/089,245 →
Method for Fabricating a Capacitor in a Dynamic Random Access Memory
Patent: 6,083,804 →
Application: 09/103,957 →
Method for Measuring the Kink Effect of a Semiconductor Device
Patent: 6,046,601 →
Application: 09/106,745 →
Method for Measuring Current Density in a Semiconductor Device with Kink Effect
Patent: 6,060,900 →
Application: 09/106,752 →
Tool for Inspecting Broken Wafer Edges
Patent: 6,101,868 →
Application: 09/107,164 →
Method of Forming a via with Plasma Treatment of Sog
Patent: 6,074,941 →
Application: 09/113,471 →
Structure of Buried Bit Line
Patent: 6,008,522 →
Application: 09/113,844 →
Method of Fabricating a Buried Bit Line
Patent: 5,882,972 →
Application: 09/114,005 →
Method for Fabricating a Via
Patent: 6,100,183 →
Application: 09/132,384 →
Method and Magnetorheological Fluid Formulations for Increasing the Output of a Magnetorheological Fluid
Patent: 6,027,664 →
Application: 09/133,148 →
Method of Fabricating Flash Electrically-Erasable and Programmable Read-Only Memory (Eeprom) Device
Patent: 6,017,796 →
Application: 09/138,757 →
Method of Fabricating Shallow Trench Isolation
Patent: 6,051,479 →
Application: 09/140,114 →
Method of Fabricating an Electrically Erasable and Programmable Read-Only Memory (Eeprom) with Improved Quality for the Tunneling Oxide Layer Therein
Patent: 5,976,935 →
Application: 09/149,587 →
Architecture of Poly Fuses
Patent: 6,150,916 →
Application: 09/149,929 →
Method for Fabricating a Shallow Trench Isolation Structure
Patent: 6,190,999 →
Application: 09/152,360 →
Method for Fabricating a Shallow Trench Isolation
Patent: 6,133,114 →
Application: 09/152,450 →
Method for Fabricating a Shallow Trench Isolation Structure
Patent: 6,001,708 →
Application: 09/164,288 →
Method of Coating Amorphous Silicon Film
Patent: 6,239,040 →
Application: 09/183,061 →
Method of Fabricating High Voltage Semiconductor Device
Patent: 6,180,471 →
Application: 09/183,062 →
Method of Fabricating a Flash Memory Cell
Patent: 6,127,223 →
Application: 09/186,743 →
Method of Mending Erosion of Bonding Pad
Patent: 6,221,752 →
Application: 09/186,744 →
Flash Memory Structure and Method of Manufacture
Patent: 6,071,776 →
Application: 09/186,748 →
Anti-Leakage Apparatus
Patent: 6,103,079 →
Application: 09/186,999 →
Structure of a Flash Memory
Patent: 6,046,938 →
Application: 09/191,326 →
Method of Forming Hemispherical Grain Polysilicon Over Lower Electrode Capacitor
Patent: 6,121,109 →
Application: 09/191,327 →
Method for Analyzing a Fabrication Machine Using Boolean Search Strategies
Application: 09/200,330 →
Publication: US 2002/0026298
Method for Fabricating a Dynamic Random Access Memory with a Vertical Pass Transistor
Patent: 5,960,282 →
Application: 09/206,065 →
Method of Fabricating a Dram Capacitor
Patent: 6,187,629 →
Application: 09/206,109 →
Method for Fabricating a Transistor
Patent: 6,130,121 →
Application: 09/206,111 →
Method of Fabricating Bit Lines by Damascene
Patent: 6,071,804 →
Application: 09/206,112 →
Method of Manufacturing a Flash Memory Structure
Patent: 6,103,577 →
Application: 09/213,345 →
Method of Fabricating Metal Oxide Semiconductor
Patent: 6,235,595 →
Application: 09/213,599 →
Method of Fabricating a Flash Memory
Patent: 6,221,718 →
Application: 09/213,600 →
Method of Fabricating a Dynamic Random Access Memory Capacitor
Patent: 6,204,108 →
Application: 09/213,783 →
Method for Bottom Electrode of Capacitor
Patent: 6,204,121 →
Application: 09/213,934 →
Method of Fabricating an Isolation Structure in an Integrated Circuit
Patent: 6,255,191 →
Application: 09/215,599 →
Method for Manufacturing Shallow Trench Isolation Structure
Patent: 6,030,882 →
Application: 09/223,200 →
Method for Forming via Hole
Patent: 6,136,694 →
Application: 09/223,330 →
Method of Fabricatingflash Erasable Programmable Read Only Memory
Patent: 6,207,504 →
Application: 09/223,337 →
Planariation Process
Patent: 6,211,097 →
Application: 09/223,398 →
Method for Forming Flash Memory Cell
Patent: 6,235,582 →
Application: 09/223,613 →
Method for Fabricating a Flash Memory
Patent: 6,232,183 →
Application: 09/227,680 →
Method for Fabricating a Flash Memory
Patent: 6,180,459 →
Application: 09/227,974 →
Method for Forming a Via
Patent: 6,274,493 →
Application: 09/227,975 →
Flash Memory Structre
Patent: 6,215,147 →
Application: 09/235,261 →
Method of Complementary Metal-Oxide Semiconductor
Patent: 6,232,162 →
Application: 09/236,932 →
Method of Forming a Shallow Trench Isolation Structure
Patent: 6,238,996 →
Application: 09/236,951 →
Method of Manufacturing Shallow Trench Isolation
Patent: 6,040,232 →
Application: 09/236,955 →
Method for Manufacturing a Cylindrical Capacitor
Patent: 6,235,576 →
Application: 09/241,522 →
Triple Well Structure
Patent: 6,111,283 →
Application: 09/241,524 →
Surface Treatment for Bonding Pad
Patent: 6,063,207 →
Application: 09/241,525 →
Method for Forming Hemispherical Silicon Grains on Designated Areas of Silicon Layer
Patent: 6,187,630 →
Application: 09/241,526 →
Method for Fabricating Contact Hole
Application: 09/241,527 →
Publication: US 2002/0068376
Method for Processing a Poly Defect
Patent: 6,183,819 →
Application: 09/241,528 →
Method for Fabricating a Flash Memory
Patent: 6,153,472 →
Application: 09/241,544 →
Damascene Process
Patent: 6,197,678 →
Application: 09/241,742 →
Etching Method for Doped Polysilicon Layer
Patent: 6,274,503 →
Application: 09/241,757 →
Method of Forming a Flash Memory Device
Patent: 6,294,428 →
Application: 09/241,759 →
Method for Forming Shallow Trench Isolation Structure
Patent: 6,001,707 →
Application: 09/241,760 →
Method for Forming Shallow Trench Isolation
Application: 09/241,789 →
Publication: US 2002/0045324
Method of Reducing Salicide Lateral Growth
Patent: 6,211,048 →
Application: 09/241,792 →
Self-Aligned Contact Process Comprising a Two-Layer Spacer Wherin One Layer Is at a Level Lower Than the Top Surface of the Gate Structure
Patent: 6,057,196 →
Application: 09/241,793 →
Method for Fabricating Shallow Trench Isolation Structure
Patent: 5,937,309 →
Application: 09/241,977 →
Method for Forming Hemispherical Grained Silicon Structure
Patent: 6,171,955 →
Application: 09/246,226 →
Method for Removing Photoresist
Patent: 6,107,205 →
Application: 09/246,737 →
Method for Forming Salicide Layers
Patent: 6,194,297 →
Application: 09/246,762 →
Method for Forming Inter-Metal Dielectrics
Patent: 6,265,298 →
Application: 09/249,882 →
Method of Fabricating Self-Aligned Silicide
Patent: 6,184,115 →
Application: 09/250,618 →
Method of Manufacturing Capacitor for Mixed-Moded Circuit Device
Patent: 6,177,327 →
Application: 09/250,628 →
Method of Fabricating Shallow Trench Isolation Using High Density Plasma Cvd
Patent: 6,191,004 →
Application: 09/250,749 →
Method of Manufacturing Bit Line
Patent: 6,087,260 →
Application: 09/252,600 →
Method for Fabricating a Shallow Trench Isolation Structure
Patent: 6,107,159 →
Application: 09/261,094 →
Method of Chemical-Mechanical Polishing
Patent: 6,171,976 →
Application: 09/261,098 →
Method of Manufacturing Flash Memory
Patent: 6,048,768 →
Application: 09/267,760 →
Method of Fabricating Barrier Layer
Patent: 6,319,826 →
Application: 09/267,875 →
Method of Manufacturing Liner Insulating Layer
Patent: 6,156,664 →
Application: 09/267,883 →
Method for Manufacturing Mos Transistor
Patent: 5,972,764 →
Application: 09/270,026 →
Method of Fabricating Dynamic Random Access Memories
Patent: 6,172,388 →
Application: 09/270,027 →
Method for Monitoring Dosage/Focus/Leveling
Patent: 6,066,419 →
Application: 09/270,278 →
Method of Fabricating Flash Memory
Patent: 6,284,597 →
Application: 09/273,067 →
Method of Fabricating a Dual Damascene Structure in an Integrated Circuit
Patent: 6,156,642 →
Application: 09/274,603 →
Semiconductor Device with an Anti-Doped Region
Application: 09/280,297 →
Method of Fabricating Dual Damascene Structure
Patent: 6,313,028 →
Application: 09/280,892 →
Publication: US 2001/0002333
Method of Fabricating Silicide Layer on Gate Electrode
Patent: 6,221,725 →
Application: 09/286,004 →
Method for Improving Wafer Topography to Provide More Accurate Transfer of Interconnect Patterns
Patent: 6,214,722 →
Application: 09/286,005 →
Method of Manufacturing Bottom Electrode of Capacitor
Patent: 6,143,603 →
Application: 09/286,021 →
Method of Manufacturing Flash Memory
Patent: 6,060,357 →
Application: 09/286,139 →
Method for Manufacturing Shallow Trench Isolation Structure
Patent: 6,232,202 →
Application: 09/286,231 →
Method for Fabricating a Flash Memory
Patent: 6,214,667 →
Application: 09/292,870 →
Self-Aligned Metal Silicide
Application: 09/293,419 →
Publication: US 2002/0011631
Method of Manufacturing Interconnect
Patent: 6,218,294 →
Application: 09/293,420 →
Fully Self-Aligned Method for Fabricating Transistor and Memory
Patent: 6,190,958 →
Application: 09/293,430 →
Method for Forming a Stacked Gate
Patent: 6,171,909 →
Application: 09/293,434 →
Method of Forming Dielectric Layer with Low Dielectric Constant
Patent: 6,319,850 →
Application: 09/294,541 →
Method of Manufacturing Bottom Electrode of Capacitor
Patent: 6,225,160 →
Application: 09/295,067 →
Method of Optical Proximity Correction
Patent: 6,120,953 →
Application: 09/298,324 →
Method for Manufacturing Cmos
Patent: 5,981,325 →
Application: 09/299,255 →
Method for Fabricating a Hybrid Isolation Structure
Application: 09/299,719 →
Publication: US 2001/0023107
Method for Fabricating Capacitor
Patent: 6,159,789 →
Application: 09/306,093 →
High Density Flash Memory Cell
Patent: 6,294,812 →
Application: 09/306,119 →
Method of Manufacturing Interconnect
Patent: 6,035,530 →
Application: 09/306,130 →
Method of Fabricating High Density Flash Memory with Self-Aligned Tunneling Window
Patent: 6,114,204 →
Application: 09/306,348 →
Transistor Structure of Esd Protection Device
Patent: 6,057,579 →
Application: 09/307,319 →
Method of Fabricating Dual Damascene
Patent: 6,017,817 →
Application: 09/309,186 →
Method for Fabricating Metal-Oxide Semiconductor Transistor
Patent: 6,150,276 →
Application: 09/313,166 →
Method for Forming Gate Terminal
Patent: 6,136,675 →
Application: 09/313,167 →
Method for Forming Conductive Line
Patent: 6,197,680 →
Application: 09/313,510 →
Method of Fabricating Flash Memory
Patent: 6,153,471 →
Application: 09/313,511 →
Method for Fabricating Passivation Layer
Patent: 6,421,108 →
Application: 09/313,516 →
Method of Fabricating Semiconductor Device
Patent: 6,194,298 →
Application: 09/315,797 →
Method of Forming a Test Key Architecture
Patent: 6,133,055 →
Application: 09/316,196 →
Method for Fabricating Inter-Metal Dielectric Layer
Patent: 6,232,214 →
Application: 09/316,475 →
Structure of Electrostatic Discharge Protection Device
Patent: 6,222,237 →
Application: 09/316,584 →
Method of Fabricating Passivation Layer in Liquid Crystal Display
Patent: 6,121,151 →
Application: 09/316,585 →
Method of Fabricating Storage Node
Patent: 6,291,295 →
Application: 09/316,979 →
Method of Fabricating Cylindrical Capacitor
Patent: 6,133,090 →
Application: 09/322,051 →
Method of Fabricating a Metal Plug of a Semiconductor Device Using a Novel Tin Barrier Layer
Application: 09/322,054 →
Publication: US 2002/0016063
Method for Fabricating Field Emission Display Cathode
Patent: 6,042,444 →
Application: 09/322,055 →
Method for Improving Stability of Anti-Coating Layer
Application: 09/325,365 →
Publication: US 2001/0003606
Metal Etching Process
Application: 09/326,380 →
Method of Fabricating Passivation of Gate Electrode
Patent: 6,197,673 →
Application: 09/328,056 →
Method for Fabricating a Gate Conductive Structure
Application: 09/328,850 →
Publication: US 2001/0046727
Method of Fabricating a Semiconductor Device
Patent: 6,274,466 →
Application: 09/328,967 →
Method for Manufacturing Even Dielectric Layer
Patent: 6,200,897 →
Application: 09/328,977 →
Method of Forming Unlanded via Hole
Patent: 6,083,825 →
Application: 09/329,113 →
Fabrication Method of a Self-Aligned Contact Window
Patent: 6,245,625 →
Application: 09/336,553 →
Method of Fabricating Conductive Line Structure
Patent: 6,274,477 →
Application: 09/336,554 →
Method of Manufacturing Interconnect
Patent: 6,133,143 →
Application: 09/340,928 →
Method for Manufacturing Metal Oxide Semiconductor Transistor Having Raised Source/Drain
Patent: 6,254,676 →
Application: 09/340,969 →
Fabrication Method of an Interconnect
Patent: 6,165,895 →
Application: 09/344,865 →
Method of Manufacturing Salicide Layer
Patent: 6,177,319 →
Application: 09/345,435 →
Method of Manufacturing Contact Pad
Patent: 6,251,769 →
Application: 09/347,180 →
Method for Forming Polysilicon Gate Electrode
Patent: 6,171,939 →
Application: 09/348,389 →
Method for Fabricating Passivation Layer on Metal Pad
Patent: 6,277,725 →
Application: 09/348,396 →
Method of Fabricating Preserve Layer
Patent: 6,303,043 →
Application: 09/348,407 →
Shallow Trench Isolation Process
Patent: 6,187,649 →
Application: 09/348,409 →
Fabrication Method of a Gate Junction Conductive Structure
Patent: 6,291,301 →
Application: 09/356,961 →
Method of Monitoring Deep Ultraviolet Exposure System
Patent: 6,278,116 →
Application: 09/370,773 →
Conveyance Arm Device
Patent: 6,302,459 →
Application: 09/372,431 →
Fabrication Method for Gate Structure Having Gate Dielectirc Layers of Different Thickness
Patent: 6,177,362 →
Application: 09/375,877 →
Method of Fabricating Flash Memory
Patent: 6,242,307 →
Application: 09/379,382 →
Method of Fabricating a Mos Transistor with Local Channel Ion Implantation Regions
Patent: 6,297,082 →
Application: 09/383,033 →
Method for Fabricating Gate Oxide Layer
Patent: 6,221,712 →
Application: 09/385,805 →
A Modified Implementation of Air-Gap Low-K Dielectric for Unlanded Via
Patent: 6,077,767 →
Application: 09/389,823 →
Method for Manufacturing Dynamic Random Access Memory
Patent: 6,228,700 →
Application: 09/389,824 →
Method for Forming Shallow Trench Isolation Structure
Patent: 6,096,623 →
Application: 09/392,924 →
Lifetime Measurement of an Ultra-Thin Dielectric Layer
Patent: 6,249,139 →
Application: 09/393,054 →
Method to Reduce Parasitic Capacitance
Patent: 6,238,987 →
Application: 09/394,636 →
Method for Manufacturing Bit Line and Bit Line Contact
Patent: 6,255,168 →
Application: 09/394,637 →
Method for Manufacturing Shallow Trench Isolation
Patent: 6,251,750 →
Application: 09/396,140 →
Method for Forming a Shallow Trench Isolation Structure
Patent: 6,344,415 →
Application: 09/397,161 →
Method of Fabricating Protection Structure
Patent: 6,291,281 →
Application: 09/406,356 →
Method of Protecting a Well at a Floating Stage
Patent: 6,245,610 →
Application: 09/406,517 →
Method Offorming a Self-Aligned Silicide Structure in Integrated Circuit Fabrication
Patent: 6,268,241 →
Application: 09/408,152 →
Retardation Layer for Preventing Diffusion of Metal Layer and Fabrication Method Therof
Patent: 6,156,655 →
Application: 09/408,612 →
Method for Increasing Surface Area of a Bottom Electrode for a Dram
Patent: 6,232,177 →
Application: 09/415,564 →
Method of Fabricating Dual Damascene Wherein the Imd Layer Comprises Fsg Formed Over a Usg Liner
Patent: 6,319,814 →
Application: 09/417,830 →
Method to Maintain Consistent Thickness of Thin Film Deposited by Chemical Vapor Deposition
Patent: 6,228,420 →
Application: 09/420,961 →
Method for Fabricating a Buried Bit Line in a Dram Cell
Patent: 6,303,424 →
Application: 09/422,577 →
Method of Forming a Flash Memory
Patent: 6,232,181 →
Application: 09/422,625 →
Method of Forming Three-Dimensional Flash Memory Structure
Patent: 6,136,650 →
Application: 09/422,626 →
Fabrication Method for Flash Memory Cell
Patent: 6,249,022 →
Application: 09/425,395 →
Method of Fabricating Self-Aligned Ultra Short Channel
Patent: 6,214,677 →
Application: 09/426,923 →
Method of Reducing a Critical Dimension of a Patterned Photoresist Layer
Patent: 6,348,301 →
Application: 09/427,793 →
Fabrication Method for Ultra Short Channel Device Comprising Self-Aligned Landing Pad
Patent: 6,248,622 →
Application: 09/427,880 →
Method for Manufacturing Two-Bit Flash Memory
Patent: 6,214,672 →
Application: 09/428,356 →
Method of Fabricating High Voltage Mos Device
Patent: 6,277,675 →
Application: 09/429,150 →
Method of Manufacturing Flash Memory
Patent: 6,271,089 →
Application: 09/433,955 →
Electrostatic Discharge Protection Circuit for Multi-Voltage Power Supply Circuit
Patent: 6,411,485 →
Application: 09/433,996 →
Fabricating Method for a Semiconductor Device Comprising Gate Oxide Layers of Various Thicknesses
Patent: 6,265,267 →
Application: 09/434,033 →
Method of Manufacturing Binary Phase Shift Mask
Patent: 6,255,023 →
Application: 09/434,046 →
Method of Self-Aligned Dram Cell
Patent: 6,159,808 →
Application: 09/437,952 →
Method to Reduce Inverse-Narrow-Width-Effect
Patent: 6,277,697 →
Application: 09/439,032 →
Fabrication Method for Self-Aligned Silicide
Application: 09/439,557 →
Method for Forming Dynamic Random Access Memory Device with an Ultra-Short Channel and an Ultra-Shallow Junction
Patent: 6,146,955 →
Application: 09/439,791 →
Fabrication Method for a Dual Damascene Comprising an Air-Gap
Patent: 6,159,840 →
Application: 09/439,930 →
Mask with Alternating Scattering Bars
Patent: 6,238,825 →
Application: 09/442,839 →
Optical Proximity Correction of L and T Patterns on Negative Photoresist
Patent: 6,080,527 →
Application: 09/442,861 →
Three-Phase Phase Shift Mask
Patent: 6,312,855 →
Application: 09/444,466 →
Multi-Layer Polysilicon Plug and Method for Making the Same
Application: 09/447,325 →
Publication: US 2002/0009850
Fabrication Method for a Two-Bit Flash Memory Cell
Patent: 6,303,439 →
Application: 09/449,297 →
Monitor Method for Testing Probe Pins
Patent: 6,281,694 →
Application: 09/449,662 →
Method of Fabricating Dynamic Random Access Memory
Patent: 6,184,082 →
Application: 09/451,136 →
Method for Forming a Stacked Capacitor
Patent: 6,200,850 →
Application: 09/451,425 →
Method of Fabricating Dynamic Random Access Memory
Patent: 6,228,711 →
Application: 09/451,426 →
Method for Forming Dual Damascene Structure
Patent: 6,258,713 →
Application: 09/454,005 →
Fluid Delivering System
Patent: 6,129,108 →
Application: 09/454,261 →
Method of Removing Polymer Residues After Tungsten Etch Back
Patent: 6,534,415 →
Application: 09/455,006 →
Publication: US 2001/0053611
Method of Removing Photoresist and Reducing Native Oxide in Dual Damascene Copper Process
Patent: 6,352,938 →
Application: 09/457,561 →
Publication: US 2001/0014529
Fabrication Method for a Shallow Trench Isolation Structure
Patent: 6,221,736 →
Application: 09/457,578 →
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest May 20, 1997
From: CHEN, HWI-HUANG; KO, JOE; HONG, GARY
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008572/0199 →
Assignment of Assignor's Interest Jun 4, 1997
From: HSIAO, CHIH-HSIANG; HSU, CHIH-CHING
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008605/0255 →
Assignment of Assignor's Interest Jul 7, 1997
From: HONG, GARY
To: UNITED SEMICONDUCTOR CORPORATION
Reel/Frame 008636/0083 →
Assignment of Assignor's Interest Aug 27, 1997
From: HONG, GARY
To: UNITED SEMICONDUCTOR CORPORATION
Reel/Frame 008702/0469 →
Assignment of Assignor's Interest Sep 11, 1997
From: LIN, CHIH-HUNG; CHOU, JIH-WEN
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008806/0172 →
Assignment of Assignor's Interest Oct 27, 1997
From: HUNG, TSUNG-YUAN; HSU, YAO-PI
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008862/0585 →
Assignment of Assignor's Interest Oct 28, 1997
From: YEH, MENG-LIN
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008862/0733 →
Assignment of Assignor's Interest Nov 12, 1997
From: HONG, GARY; WANG, PATRICK; TING, WENCHI
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008892/0732 →
Assignment of Assignor's Interest Nov 25, 1997
From: LEE, CLAYMENS
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008900/0008 →
Assignment of Assignor's Interest Dec 16, 1997
From: CHEN, TIEN-YA; TSENG, CHEN-CHIU
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008927/0483 →
Assignment of Assignor's Interest Dec 18, 1997
From: CHEN, HWI-HUANG; HONG, GARY
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008941/0043 →
Assignment of Assignor's Interest Dec 24, 1997
From: SHEU, YAU-KAE
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008942/0956 →
Assignment of Assignor's Interest Dec 24, 1997
From: SHEU, YAU-KAE
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008945/0626 →
Assignment of Assignor's Interest Dec 24, 1997
From: HONG, GARY; KO, JOE
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008942/0795 →
Assignment of Assignor's Interest Dec 29, 1997
From: HONG, GARY
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008944/0139 →
Assignment of Assignor's Interest Dec 29, 1997
From: HSIEH, CHI-KUO
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008942/0944 →
Assignment of Assignor's Interest Dec 29, 1997
From: HONG, GARY
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008945/0997 →
Assignment of Assignor's Interest Dec 30, 1997
From: SHEU,YAU-KAE
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008950/0618 →
Assignment of Assignor's Interest Dec 30, 1997
From: YU, CHIA-CHIEH
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008951/0744 →
Assignment of Assignor's Interest Feb 13, 1998
From: HONG, GARY; CHEN, ANCHOR
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008990/0390 →
Assignment of Assignor's Interest Feb 13, 1998
From: LIU, TSAN-WEN
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 008990/0721 →
Assignment of Assignor's Interest May 1, 1998
From: HONG, GARY
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 009148/0415 →
Assignment of Assignor's Interest May 4, 1998
From: SHEU, YAU-KAE; HONG, GARY
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 009149/0382 →
Assignment of Assignor's Interest May 11, 1998
From: HONG, GARY
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 009243/0184 →
Assignment of Assignor's Interest Jun 4, 1998
From: HSIAO, CHIH-HSIANG
To: UNITED SEMICONDUCTOR CORP.
Reel/Frame 009231/0320 →